Sense amplifier with lower offset and increased speed

ABSTRACT

Methods and apparatus for sensing a memory cell using lower offset, higher speed sense amplifiers are described. A sense amplifier may include an amplifier component that is configurable to operate in an amplifier mode or a latch mode. In some examples, the amplifier component may be configured to operate in the amplifier or latch mode by activating or deactivating switching components inside the amplifier component. When configured to operate in the amplifier mode, the amplifier component may be used, during a read operation of a memory cell, to pre-charge a digit line and/or amplify a signal received from the memory cell. When configured to operate in the latch mode, the amplifier component may be used to latch a state of the memory cell. In some cases, the amplifier component may use some of the same internal circuitry for pre-charging the digit line, amplifying the signal, and/or latching the state.

CROSS REFERENCE

The present Application for Patent is a continuation of U.S. patentapplication Ser. No. 15/957,790 by Guo et al., entitled “Sense AmplifierWith Lower Offset and Increased Speed,” filed Apr. 19, 2018, assigned tothe assignee hereof, and is expressly incorporated by reference in itsentirety herein.

BACKGROUND

The following relates generally to memory systems and more specificallyto sense amplifiers with lower offset and higher speed for sensingmemory cells.

Memory devices are widely used to store information in variouselectronic devices such as computers, wireless communication devices,cameras, digital displays, and the like. Information is stored byprograming different states of a memory device. For example, binarymemory devices have two logic states, often denoted by a logic “1” or alogic “0.” In other memory devices, more than two logic states may bestored. To access the stored information, a component of the electronicdevice may read, or sense, the stored logic state in the memory device.To store information in a memory cell of a memory device, a component ofthe electronic device may write, or program, the logic state in thememory cell.

Various types of memory devices exist, including those that employmagnetic hard disks, random access memory (RAM), read only memory (ROM),dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM(FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phasechange memory (PCM), and others. Memory devices may be volatile ornon-volatile. Non-volatile memory, such as PCM and FeRAM, may maintainstored logic states for extended periods of time even in the absence ofan external power source. Volatile memory devices, such as DRAM, maylose stored logic states over time unless they are periodicallyrefreshed by a power source. In some cases, non-volatile memory may usesimilar device architectures as volatile memory but may havenon-volatile properties by employing such physical phenomena asferroelectric capacitance or different material phases.

Approaches for improving memory devices may include increasing memorycell density, increasing read/write speeds, increasing reliability,increasing data retention, reducing power consumption, or reducingmanufacturing costs, among other metrics. In some cases, various circuitcomponents may be included in a sense amplifier for sensing and latchinga logic state of a memory cell. Some such components may limit the speedof memory read operations and/or increase the size or power consumptionassociated with the sense amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example memory device that supports senseamplifiers with lower offset and higher speed for sensing memory cellsin accordance with examples of the present disclosure.

FIG. 2 illustrates an example circuit that supports sense amplifierswith lower offset and higher speed for sensing memory cells inaccordance with examples of the present disclosure.

FIG. 3 illustrates an example of non-linear electrical properties withhysteresis plots for a memory cell that supports sense amplifiers withlower offset and higher speed for sensing memory cells in accordancewith examples of the present disclosure.

FIG. 4 illustrates an example of a circuit that supports senseamplifiers with lower offset and higher speed for sensing memory cellsin accordance with examples of the present disclosure.

FIG. 5 illustrates an example of a circuit that supports senseamplifiers with lower offset and higher speed for sensing memory cellsin accordance with examples of the present disclosure.

FIG. 6 illustrates an example of a circuit that supports senseamplifiers with lower offset and higher speed for sensing memory cellsin accordance with examples of the present disclosure.

FIG. 7 illustrates an example of a circuit that supports senseamplifiers with lower offset and higher speed for sensing memory cellsin accordance with examples of the present disclosure.

FIG. 8 illustrates an example of a circuit that supports senseamplifiers with lower offset and higher speed for sensing memory cellsin accordance with examples of the present disclosure.

FIG. 9 illustrates an example of a circuit that supports senseamplifiers with lower offset and higher speed for sensing memory cellsin accordance with examples of the present disclosure.

FIG. 10 illustrates an example of a circuit that supports senseamplifiers with lower offset and higher speed for sensing memory cellsin accordance with examples of the present disclosure.

FIG. 11 shows a timing diagram illustrating operations of an exampleread operation that supports sense amplifiers with lower offset andhigher speed for sensing memory cells in accordance with variousexamples of the present disclosure.

FIG. 12 illustrates an example of a circuit that supports senseamplifiers with lower offset and higher speed for sensing memory cellsin accordance with examples of the present disclosure.

FIG. 13 illustrates an example of a circuit that supports senseamplifiers with lower offset and higher speed for sensing memory cellsin accordance with examples of the present disclosure.

FIG. 14 illustrates an example of a circuit that supports senseamplifiers with lower offset and higher speed for sensing memory cellsin accordance with examples of the present disclosure.

FIG. 15 shows a block diagram of a memory device that may support senseamplifiers with lower offset and higher speed for sensing memory cellsin accordance with various examples of the present disclosure.

FIG. 16 shows a block diagram of a memory controller that may supportsense amplifiers with lower offset and higher speed for sensing memorycells in accordance with various examples of the present disclosure.

FIG. 17 shows a diagram of a system including a device that may supportsense amplifiers with lower offset and higher speed for sensing memorycells in accordance with various examples of the present disclosure.

FIG. 18 shows a flowchart illustrating a method that may support senseamplifiers with lower offset and higher speed for sensing memory cellsin accordance with various examples of the present disclosure.

DETAILED DESCRIPTION

The logic state of a memory cell may be detected using a read operationthat employs various schemes (e.g., those related to a sense amplifier)for sensing and latching the logic state of memory cells in accordancewith aspects of the present disclosure. For example, a memory device mayinclude a sense amplifier that is coupled with a memory cell to senseand latch the logic state of the memory cell. The state of the memorycell may then be provided to other circuitry in the memory device andtransmitted to other components.

In some cases, a memory device may include a cascode device topre-charge a digit line during a read operation before coupling a memorycell with the digit line, and/or to couple the digit line with anamplifier during signal development. However, a cascode device used inthis manner may operate in a sub-threshold regime, which may introducenoise into the read operation (e.g., via the digit line). As describedherein, alternative schemes for pre-charging a digit line and/or sensingand latching the state of a memory cell may provide advantages relativeto approaches based on the use of a cascode or other approaches, bypotentially speeding up the latch operation and reducing the amount oflatch circuitry required

In some cases, a sense amplifier may include an amplifier component thatmay be configurable (e.g., using switching components in the amplifiercomponent) to operate in either an amplifier mode (e.g., to operate in amanner similar to a differential amplifier or other type of amplifier)or a latch mode (e.g., to operate in a manner similar to a latchcircuit).

When the amplifier component is configured to operate in the amplifiermode, it may be able to aid in pre-charging the digit line to an initialsense voltage (instead of, for example, using a cascode device forpre-charging the digit line). In the amplifier component mode, theamplifier component may also be able to aid in amplifying the signalreceived from the memory cell.

When the amplifier component is configured in the latch mode, it may beable to aid in latching the state of the memory cell (e.g., in additionto or instead of using a separate latch circuit).

Using the same amplifier component for multiple functions as describedabove may have several benefits relative to, for example, acascode-based implementation. For example, using the amplifier componentboth to pre-charge the digit line to an initial sensing voltage and tolatch the state may increase the speed at which the state can be latchedby compensating for the voltage offset introduced by the amplifiercomponent during the signal development, thereby enabling the latchtrigger point to track the developing signal more closely. In addition,re-using transistors and other circuitry in the amplifier component formultiple, distinct functions may eliminate the need for separate latchcircuitry (in some examples), thereby potentially reducing the area andpower consumption associated with the memory device.

Features of the disclosure introduced above are further described withrespect to FIGS. 1 through 3 in the context of memory arrays, memorycircuits, and memory cell behaviors that support sense amplifiers forsensing memory cells with lower offset and higher speed. Specificexamples are then described with respect to FIGS. 4-14, which illustratecircuits and associated read operation timing diagrams that supportsense amplifiers with lower offset and higher speed for sensing memorycells. These and other features of the disclosure are further describedwith respect to FIGS. 15-18, which illustrate apparatus diagrams, systemdiagrams, and flowcharts that support sense amplifier schemes forsensing memory cells.

FIG. 1 illustrates an example memory device 100 that supports senseamplifiers with lower offset and higher speed for sensing memory cellsin accordance with various examples of the present disclosure. Thememory device 100 may also be referred to as an electronic memoryapparatus. The memory device 100 may include memory cells 105 that areprogrammable to store different logic states. In some cases, a memorycell 105 may be programmable to store two logic states, denoted a logic0 and a logic 1. In some cases, a memory cell 105 may be programmable tostore more than two logic states. In various examples, the memory cells105 may include a capacitive memory element, a ferroelectric memoryelement, a resistive element, or a self-selecting memory element.

In some examples, a memory cell 105 may store an electric chargerepresentative of the programmable logic states (e.g., storing charge ina capacitor). In one example, a charged and uncharged capacitor mayrepresent two logic states, respectively. In another example, apositively and negatively charged capacitor may represent two logicstates, respectively. DRAM or FeRAM architectures may use such designs,and the capacitor employed may include a dielectric material with linearor para-electric electric polarization properties as an insulator. Insome examples, different levels of charge of a capacitor may representdifferent logic states (e.g., supporting more than two logic states in arespective memory cell 105). In some examples, such as FeRAMarchitectures, a memory cell 105 may include a ferroelectric capacitorhaving a ferroelectric material as an insulating layer between terminalsof the capacitor. Different levels of polarization of a ferroelectriccapacitor may represent different logic states (e.g., supporting two ormore logic states in a respective memory cell 105). Ferroelectricmaterials have non-linear polarization properties including thosediscussed in further detail with reference to FIG. 3.

In some examples, a memory cell 105 may include a material portion,which may be referred to as a memory element, a memory storage element,a self-selecting memory element, or a self-selecting memory storageelement. The material portion may have a variable and configurableelectrical resistance that is representative of different logic states.

For example, a material that can take the form of a crystalline atomicconfiguration or an amorphous atomic configuration (e.g., able tomaintain either a crystalline state or an amorphous state over anambient operating temperature range of the memory device 100) may havedifferent electrical resistances depending on the atomic configuration.A more-crystalline state of the material (e.g., a single crystal, acollection of a relatively large crystal grains that is substantiallycrystalline) may have a relatively low electrical resistance, and mayalternatively be referred to as a “SET” logic state. A more-amorphousstate of the material (e.g., an entirely amorphous state, somedistribution of relatively small crystal grains that is substantiallyamorphous) may have a relatively high electrical resistance, and mayalternatively be referred to as a “RESET” logic state. Thus, a voltageapplied to such a memory cell 105 may result in different current flowdepending on whether the material portion of the memory cell 105 is inthe more-crystalline or the more-amorphous state. Accordingly, themagnitude of the current resulting from applying a read voltage to thememory cell 105 may be used to determine a logic state stored by memorycell 105.

In some examples, a memory element may be configured with various ratiosof crystalline and amorphous areas (e.g., varying degrees of atomicorder and disorder) that may result in intermediate resistances, whichmay represent different logic states (e.g., supporting two or more logicstates in a respective memory cell 105). Further, in some examples, amaterial or a memory element may have more than two atomicconfigurations, such as an amorphous configuration and two differentcrystalline configurations. Although described herein with reference toan electrical resistance of different atomic configurations, a memorydevice may use some other characteristic of a memory element todetermine a stored logic state corresponding to an atomic configuration,or combination of atomic configurations.

In some cases, a memory element in a more-amorphous state may beassociated with a threshold voltage, where electrical current flowsthrough the memory element when the threshold voltage is exceed acrossthe memory element. When a voltage applied across the memory element inthe more-amorphous state is less than the threshold voltage, current maynot flow through the memory element. In some cases, a memory element inthe more-crystalline state may not be associated with a thresholdvoltage (e.g., may be associated with a threshold voltage of zero), anda current may flow through the memory element in response to a non-zerovoltage across the memory element. In some cases, a material in both themore-amorphous state and the more-crystalline state may be associatedwith threshold voltages. For example, self-selecting memory may enhancedifferences in a threshold voltage of the memory cell between differentprogrammed states (e.g., by way of different compositionaldistributions). The logic state of a memory cell 105 having such amemory element may be set by heating the memory element to a temperatureprofile over time that supports forming a particular atomicconfiguration, or combination of atomic configurations.

A memory device 100 may include a three-dimensional (3D) memory array,where a plurality of two-dimensional (2D) memory arrays (e.g., decks,levels) are formed on top of one another. Such an arrangement mayincrease the number of memory cells 105 that may be placed or created ona single die or substrate as compared with 2D arrays, which in turn mayreduce production costs or increase the performance of a memory device100, or both. The decks may be separated by an electrically insulatingmaterial. Each deck or level may be aligned or positioned so that memorycells 105 may be approximately aligned with one another across eachdeck, forming a stack of memory cells 105.

In the example of memory device 100, each row of memory cells 105 iscoupled with one of a plurality of first access lines 110 (e.g., a wordline (WL), such as one of WL_1 through WL_M), and each column of memorycells 105 is coupled with one of a plurality of second access lines 115(e.g., a digit line (DL), such as one of DL_1 through DL_N). In somecases, first access lines 110 and second access lines 115 may besubstantially perpendicular to one another in the memory device 100(e.g., when viewing a plane of a deck of the memory device 100, as shownin FIG. 1). References to word lines and bit lines, or their analogues,are interchangeable without loss of understanding or operation.

In general, one memory cell 105 may be located at the intersection of(e.g., coupled with, coupled between) an access line 110 and an accessline 115. This intersection may be referred to as an address of a memorycell 105. A target memory cell 105 may be a memory cell 105 located atthe intersection of an energized or otherwise selected access line 110and an energized or otherwise selected access line 115. In other words,an access line 110 and an access line 115 may be energized or otherwiseselected to access (e.g., read, write) a memory cell 105 at theirintersection. Other memory cells 105 that are in electroniccommunication with (e.g., connected to) the same access line 110 or 115may be referred to as untargeted memory cells 105.

Although the access lines described with reference to FIG. 1 are shownas direct lines between memory cells 105 and coupled components, accesslines may include other circuit elements, such as capacitors, resistors,transistors, amplifiers, voltage sources, switching components,selection components, and others, which may be used to support accessoperations including those described herein. In some examples, anelectrode may be coupled with (e.g., between) a memory cell 105 and anaccess line 110, or with (e.g., between) a memory cell 105 and an accessline 115. The term electrode may refer to an electrical conductor, orother electrical interface between components, and in some cases, may beemployed as an electrical contact to a memory cell 105. An electrode mayinclude a trace, wire, conductive line, conductive layer, conductivepad, or the like, that provides a conductive path between elements orcomponents of memory device 100.

In some architectures, the logic storing component (e.g., a capacitivememory element, a ferroelectric memory element, a resistive memoryelement, other memory element) of a memory cell 105 may be electricallyisolated from a second access line 115 by a cell selection component. Afirst access line 110 may be coupled with and may control the cellselection component of the memory cell 105. For example, the cellselection component may be a transistor and the first access line 110may be coupled with a gate of the transistor. Activating the firstaccess line 110 of a memory cell 105 may result in an electricalconnection or closed circuit between the logic storing component of thememory cell 105 and its corresponding second access line 115. The secondaccess line 115 may then be accessed to read or write the memory cell105.

In some examples, memory cells 105 may also be coupled with one of aplurality of third access lines 120 (e.g., a plate line (PL), such asone of PL_1 through PL_N). In some examples, the plurality of thirdaccess lines 120 may couple memory cells 105 with one or more voltagesources for various sensing and/or writing operations including thosedescribed herein. For example, when a memory cell 105 employs acapacitor for storing a logic state, a second access line 115 mayprovide access to a first terminal of the capacitor, and a third accessline 120 may provide access to a second terminal of the capacitor (e.g.,a terminal associated with an opposite plate of the capacitor as opposedto the first terminal of the capacitor, a terminal otherwise on theopposite side of a capacitance from the first terminal of thecapacitor). Although the plurality of third access lines 120 of thememory device 100 are shown as substantially parallel with the pluralityof second access lines 115, in other examples a plurality of thirdaccess lines 120 may be substantially parallel with the plurality offirst access lines 110, or in any other configuration.

Access operations such as reading, writing, and rewriting may beperformed on a memory cell 105 by activating or selecting a first accessline 110, a second access line 115, and/or a third access line 120coupled with the memory cell 105, which may include applying a voltage,a charge, or a current to the respective access line. Access lines 110,115, and 120 may be made of conductive materials, such as metals (e.g.,copper (Cu), silver (Ag), aluminum (Al), gold (Au), tungsten (W),titanium (Ti)), metal alloys, carbon, or other conductive orsemi-conductive materials, alloys, or compounds. Upon selecting a memorycell 105, a resulting signal may be used to determine the stored logicstate. For example, a memory cell 105 with a capacitive memory elementstoring a logic state may be selected, and the resulting flow of chargevia an access line and/or resulting voltage of an access line may bedetected to determine the programmed logic state stored by the memorycell 105.

Accessing memory cells 105 may be controlled through a row decoder 125and a column decoder 135. For example, a row decoder 125 may receive arow address from the memory controller 150 and activate the appropriatefirst access line 110 based on the received row address. Similarly, acolumn decoder 135 may receive a column address from the memorycontroller 150 and activate the appropriate second access line 115.Thus, in some examples, a memory cell 105 may be accessed by activatinga first access line 110 and a second access line 115.

In some examples, the memory controller 150 may control the operation(e.g., read operations, write operations, rewrite operations, refreshoperations, discharge operations) of memory cells 105 through thevarious components (e.g. row decoder 125, column decoder 135, sensecomponent 130). In some cases, one or more of the row decoder 125,column decoder 135, and sense component 130 may be co-located orotherwise included with the memory controller 150. The memory controller150 may generate row and column address signals to activate a desiredaccess line 110 and access line 115. The memory controller 150 may alsogenerate or control various voltages or currents used during theoperation of memory device 100. For example, the memory controller 150may apply a discharge voltage to an access line 110 or an access line115 after accessing one or more memory cells 105.

In general, the amplitude, shape, or duration of an applied voltage,current, or charge may be adjusted or varied, and may be different forthe various operations discussed in operating the memory device 100.Further, one, multiple, or all memory cells 105 within memory device 100may be accessed simultaneously. For example, multiple or all memorycells 105 of memory device 100 may be accessed simultaneously during areset operation in which all memory cells 105, or a group of memorycells 105, are set to a single logic state.

A memory cell 105 may be read (e.g., sensed) by a sense component 130when the memory cell 105 is accessed (e.g., in cooperation with thememory controller 150) to determine a logic state stored by the memorycell 105. For example, the sense component 130 may be configured tosense a current or charge through the memory cell 105, or a voltageresulting from coupling the memory cell 105 with the sense component 130or other intervening component responsive to a read operation. The sensecomponent 130 may provide an output signal indicative of the logic statestored by the memory cell 105 to one or more components (e.g., to thecolumn decoder 135, the input/output component 140, the memorycontroller 150).

In some examples, after accessing the memory cell 105, the logic storageportion of memory cell 105 may discharge, or otherwise permit electricalcharge or current to flow via its corresponding access line 115. Suchcharge or current may result from biasing, or applying a voltage, to thememory cell 105 from one or more voltage sources or supplies (not shown)of the memory device 100, where such voltage sources or supplies may bepart of the sense component 130, the memory controller 150, or someother component (e.g., a biasing component). In some examples, adischarge of a memory cell 105 may cause a change in the voltage of theaccess line 115, which the sense component 130 may compare to areference voltage to determine the stored state of the memory cell 105.In some examples, a discharge of a memory cell 105 may cause a change inthe voltage of an amplifier capacitor (not shown) that is coupled withaccess line 115, and the sense component 130 may compare the voltageacross the amplifier capacitor with a reference voltage to determine thestored state of the memory cell 105.

A sense component 130 may include various switching components,selection components, transistors, amplifiers, capacitors, resistors, orvoltage sources to detect and amplify a difference in sensing signals(e.g., a difference between a read voltage and a reference voltage, adifference between a read current and a reference current, a differencebetween a read charge and a reference charge). In some examples, a sensecomponent 130 may include a collection of components (e.g., circuitelements) that may be repeated for each of a set of access lines 115connected to the sense component 130. For example, a sense component 130may include a separate sensing circuit (e.g., a separate senseamplifier, and/or a separate signal development circuit) for each of aset of access lines 115 coupled with the sense component 130, such thata logic state may be separately detected for a respective memory cell105 coupled with a respective one of the set of access lines 115. Invarious examples, a reference signal source or generated referencesignal may be shared between components of the memory device 100 (e.g.,shared among one or more sense components 130, shared among separatesensing circuits of a sense component 130).

The sense component 130 may be included in a device that includes thememory device 100. For example, the sense component 130 may be includedwith other read and write circuits, decoding circuits, or registercircuits of the memory that may be coupled with the memory device 100.In some examples, the detected logic state of a memory cell 105 may beoutput through a column decoder 135 as an output. In some examples, asense component 130 may be part of a column decoder 135 or a row decoder125. In some examples, a sense component 130 may be connected to orotherwise in electronic communication with a column decoder 135 or a rowdecoder 125.

Although a single sense component 130 is shown, a memory device 100 mayinclude more than one sense component 130. For example a first sensecomponent 130 may be coupled with a first subset of access lines 115 anda second sense component 130 may be coupled with a second subset ofaccess lines 115 (e.g., different from the first subset of access lines115). In some examples, such a division of sense components 130 maysupport parallel (e.g., simultaneous) operation of multiple sensecomponents 130.

In some memory architectures, accessing the memory cell 105 may degradeor destroy the stored logic state and re-write or refresh operations maybe performed to return the original logic state to memory cell 105. InDRAM or FeRAM, for example, a capacitor of a memory cell 105 may bepartially or completely discharged during a sense operation, therebycorrupting the logic state that was stored in the memory cell 105. InPCM, for example, sense operations may cause a change in the atomicconfiguration of a memory cell 105, thereby changing the resistancestate of the memory cell 105. Thus, in some examples, the logic statestored in a memory cell 105 may be rewritten after an access operation.Further, activating a single access line 110 or 115 may result in thedischarge of all memory cells 105 coupled with the access line 110 or115. Thus, several or all memory cells 105 coupled with an access line110 or 115 of an access operation (e.g., all cells of an accessed row,all cells of an accessed column) may be rewritten after the accessoperation.

In some examples, reading a memory cell 105 may be non-destructive. Thatis, the logic state of the memory cell 105 may not need to be rewrittenafter the memory cell 105 is read. For example, in non-volatile memorysuch as PCM, accessing the memory cell 105 may not destroy the logicstate and, thus, the memory cell 105 may not require rewriting afteraccessing. However, in various examples, refreshing the logic state ofthe memory cell 105 may or may not be needed in the absence of accessoperations. For example, the logic state stored by a memory cell 105 maybe refreshed at periodic intervals by applying an appropriate write orrefresh pulse to maintain the stored logic state. Refreshing the memorycell 105 may reduce or eliminate read disturb errors or logic statecorruption due to a charge leakage or a change in an atomicconfiguration of a memory element over time.

A memory cell 105 may also be set, or written, by activating therelevant first access line 110, second access line 115, and/or thirdaccess line 120. In other words, a logic state may be stored in thememory cell 105. Column decoder 135 or row decoder 125 may accept data,for example via input/output component 140, to be written to the memorycells 105.

In the case of a capacitive memory element, a memory cell 105 may bewritten by applying a voltage to the capacitor, and then isolating thecapacitor (e.g., isolating the capacitor from a voltage source used towrite the memory cell 105) to store a charge in the capacitor associatedwith a desired logic state. In the case of ferroelectric memory, aferroelectric memory element (e.g., a ferroelectric capacitor) of amemory cell 105 may written by applying a voltage with a magnitude highenough to polarize the ferroelectric memory element (e.g., applying asaturation voltage) with a polarization associated with a desired logicstate, and the ferroelectric memory element may be isolated (e.g.,floating), or a zero net voltage may be applied across the ferroelectricmemory element (e.g., grounding, virtually grounding the ferroelectricmemory element). In the case of PCM, a memory element may be written byapplying a current with a profile that causes (e.g., by way of heatingand cooling) the memory element to form an atomic configurationassociated with a desired logic state.

In various examples in accordance with the present disclosure, a senseamplifier may be provided, such as a sense amplifier within sensecomponent 130, to support lower offset and higher speed sensing ofsignals to determine and latch a logic state stored by a memory cell105. The sense amplifier may, in some examples, include an amplifiercomponent that may be configurable (e.g., using switching componentsinside the amplifier component) to operate in multiple different modes.By including a sense amplifier having a configurable amplifier componentsuch as those described herein, the memory device 100 may supportparticular techniques for sensing and latching a logic state stored by amemory cell 105 with a lower offset and higher speed, such as thosedescribed with respect to FIGS. 4-14.

The described implementations of a sense amplifier having a configurableamplifier component may enable faster and more accurate latching of astate of a memory cell. Further, the described implementations of asense amplifier having a configurable amplifier component may support asmaller memory cell footprint (e.g., supporting fewer components such asfewer transistors and fewer or smaller latches), may support fasteraccess operations, and/or may provide other benefits including thosedescribed herein.

FIG. 2 illustrates a simplified example circuit 200 that supports senseamplifiers with lower offset and higher speed for sensing memory cellsin accordance with various examples of the present disclosure. Circuit200 may include a memory cell 105-a and a sense amplifier 225, which maybe examples of a memory cell 105 and a sense component 130 (or a portionof a sense component 130) described with reference to FIG. 1. Circuit200 may also include a word line 205, a digit line 210, and a plate line215, which, in some examples, may correspond to a first access line 110,a second access line 115, and a third access line 120, respectively, asdescribed with reference to FIG. 1. The circuit 200 may also include areference line 255 that may be used by sense amplifier 225 a todetermine a stored logic state of the memory cell 105-a.

As illustrated in FIG. 2, the sense amplifier 225 may include a firstinput node 230 and a second input node 240, which in various examplesmay be coupled with different access lines of a circuit (e.g., withdigit line 210 and reference line 255 of circuit 200, respectively).Other configurations of access lines and/or reference lines, however,are possible in accordance with various examples of the presentdisclosure. In some examples, deactivating switching component 260isolates sense amplifier 225 from the digit line 210.

Sense amplifier 225 may be coupled with one or more voltage sources 235.In some examples, sense amplifier 225 may be coupled with voltage source235-a that provides a high voltage (e.g., a voltage of V_(H), which maybe set to a supply voltage such as V_(SS)). In some examples, senseamplifier 225 may be coupled with voltage source 235-b that provides alow voltage (e.g., a voltage of V_(L), which may be a ground voltagesubstantially equal to V₀ or a negative voltage). In some examples,sense amplifier 225 may be coupled with a reference voltage source 235-cthat provides a reference voltage V_(REF) that is used to determine alogic state of memory cell 105-a.

In some examples, digit line 210 and/or sense amplifier 225 may becoupled with a pre-charge voltage source (not shown) that is used topre-charge digit line 210 to a first voltage. In some examples, digitline 210 and/or sense amplifier 225 may be coupled with a sense voltagesource (not shown) that is used to pre-charge digit line 210 to a secondvoltage using an amplifier component in sense amplifier 225. In someexamples, a single variable voltage source may be configured toselectively provide some or all of a reference voltage, a pre-chargevoltage, and a sense voltage.

Memory cell 105-a a may include a logic storage component (e.g., amemory element), such as capacitor 220 that has a first plate (e.g.,cell plate 221), and a second plate (e.g., cell bottom 222). The cellplate 221 and the cell bottom 222 may be capacitively coupled through adielectric material positioned between them (e.g., in a DRAMapplication), or capacitively coupled through a ferroelectric materialpositioned between them (e.g., in a FeRAM application). The cell plate221 may be associated with a voltage Vplate, and cell bottom 222 may beassociated with a voltage Vbottom, as illustrated in the circuit 200. Insome examples, the orientation of cell plate 221 and cell bottom 222 maybe different (e.g., flipped) without changing the operation of thememory cell 105-a. The cell plate 221 may be accessed via the plate line215 and cell bottom 222 may be accessed via the digit line 210. Asdescribed herein, various states may be stored by charging, discharging,and/or polarizing the capacitor 220.

The capacitor 220 may be in electronic communication with the digit line210, and the stored logic state of capacitor 220 may be read or sensedby operating various elements represented in circuit 200. For example,the memory cell 105-a a may also include a cell selection component 245,and the capacitor 220 can be coupled with digit line 210 when cellselection component 245 is activated (e.g., by way of an activatinglogical signal), and the capacitor 220 can be isolated from digit line210 when cell selection component 245 is deactivated (e.g., by way of adeactivating logical signal).

In some examples, activating the cell selection component 245 may bereferred to as selecting the memory cell 105-a, and deactivating thecell selection component 245 may be referred to as deselecting thememory cell 105-a. In some examples, the cell selection component 245may be or include a transistor and its operation may be controlled byapplying an activation voltage to the transistor gate, where the voltagefor activating the transistor (e.g., the voltage between the transistorgate terminal and the transistor source terminal) may be greater thanthe threshold voltage magnitude of the transistor. The word line 205 maybe used to activate the cell selection component 245. For example, aselection voltage applied to the word line 205 (e.g., a word linelogical signal) may be applied to the gate of a transistor of cellselection component 245, which may connect the capacitor 220 with thedigit line 210 (e.g., providing a conductive path between the capacitor220 and the digit line 210).

In other examples, the positions of the cell selection component 245 andthe capacitor 220 in the memory cell 105-a may be switched, such thatcell selection component 245 is coupled with or between the plate line215 and the cell plate 221, and the capacitor 220 is coupled with orbetween the digit line 210 and the other terminal of the cell selectioncomponent 245. In such an example, the cell selection component 245 mayremain in electronic communication with the digit line 210 through thecapacitor 220. This configuration may be associated with alternativetiming and biasing for access operations.

In example memory cells that employ a capacitor 220 that is aferroelectric capacitor, the capacitor 220 may or may not fullydischarge upon connection to the digit line 210. In various schemes, tosense the logic state stored by a ferroelectric capacitor 220, a voltagemay be applied to the plate line 215 and/or the digit line 210, and theword line 205 may be biased to select the memory cell 105-a. In somecases, the plate line 215 and/or the digit line 210 may be virtuallygrounded and then isolated from the virtual ground, which may bereferred to as a floating condition, prior activating the word line 205.

Operation of the memory cell 105-a by varying the voltage to cell plate221 (e.g., via the plate line 215) may be referred to as “moving thecell plate.” Biasing the plate line 215 and/or the digit line 210 mayresult in a voltage difference (e.g., the voltage of the digit line 210minus the voltage of the plate line 215) across the capacitor 220. Thevoltage difference may accompany a change in the stored charge oncapacitor 220, where the magnitude of the change in stored charge maydepend on the initial state of the capacitor 220 (e.g., whether theinitial logic state stored a logic 1 or a logic 0). In some schemes, thechange in the stored charge of the capacitor 220 may cause a change inthe voltage of the digit line 210, which may be used by a senseamplifier 225 (e.g., in sense component 130) to determine the storedlogic state of the memory cell 105-a.

The resulting voltage of the digit line 210 after selecting the memorycell 105-a may be compared to a reference (e.g., a voltage of referenceline 210, V_(REF), which may be supplied by voltage source 235-c) by thesense amplifier 225 to determine the logic state that was stored in thememory cell 105-a. In some cases, sense amplifier 225 may include anamplifier capacitor (not shown) that is configured to be selectivelycoupled with digit line 210 to enable electric charge to be transferredbetween memory cell 105-a and the amplifier capacitor during a readoperation. In this case, sense amplifier 225 may compare the voltage ofthe amplifier capacitor with the voltage of reference line 255 todetermine the logic state of the memory cell.

Other operations may be used to support selecting and/or sensing thememory cell 105-a, including operations for supporting sense amplifiers(e.g., sense amplifier 225) with lower offset and higher speed forsensing memory cells as described herein.

Sense amplifier 225 may include various transistors or amplifiers topre-charge the digit line 210 during a pre-charging portion of a readoperation, to detect and amplify a difference in signals during a signaldevelopment portion of the read operation, to determine a state of thememory cell based on the difference in the signals, and to latch thestate, which may include storing the state within the sense amplifier225 itself or within a latch circuit that is external to the senseamplifier. In some examples, sense amplifier 225 may include anamplifier component (not shown) that is configurable to operate indifferent modes during various portions of a read operation.

In some cases, the state may be output from the sense amplifier at anoutput node 250 via one or more input/output (I/O) lines (e.g., I/O line265), which may include an output through a column decoder 135 viainput/output component 140 described with reference to FIG. 1.

The circuit 200, including the sense amplifier 225 and the cellselection component 245, may include various types of transistors. Forexample, the circuit 200 may include n-type transistors, where applyinga relative positive voltage to the gate of the n-type transistor that isabove a threshold voltage for the n-type transistor (e.g., an appliedvoltage having a positive magnitude, relative to a source terminal, thatis greater than a threshold voltage) enables a conductive path betweenthe other terminals of the n-type transistor (e.g., the source terminaland a drain terminal).

In some examples, the n-type transistor may act as a switchingcomponent, where the applied voltage is a logical signal that is used toenable conductivity through the transistor by applying a relatively highlogical signal voltage (e.g., a voltage corresponding to a logic 1state, which may be associated with a positive logical signal voltagesupply), or to disable conductivity through the transistor by applying arelatively low logical signal voltage (e.g., a voltage corresponding toa logic 0 state, which may be associated with a ground or virtual groundvoltage). In various examples where a n-type transistor is employed as aswitching component, the voltage of a logical signal applied to the gateterminal may be selected to operate the transistor at a particularworking point (e.g., in a saturation region or in an active region).

In some examples, the behavior of a n-type transistor may be morecomplex than a logical switching, and selective conductivity across thetransistor may also be a function of varying source and drain voltages.For example, the applied voltage at the gate terminal may have aparticular voltage level (e.g., a clamping voltage) that is used toenable conductivity between the source terminal and the drain terminalwhen the source terminal voltage is below a certain level (e.g., belowthe gate terminal voltage minus the threshold voltage). When the voltageof the source terminal voltage or drain terminal voltage rises above thecertain level, the n-type transistor may be deactivated such that theconductive path between the source terminal and drain terminal isopened.

Additionally or alternatively, the circuit 200 may include p-typetransistors, where applying a relative negative voltage to the gate ofthe p-type transistor that is above a threshold voltage for the p-typetransistor (e.g., an applied voltage having a negative magnitude,relative to a source terminal, that is greater than a threshold voltage)enables a conductive path between the other terminals of the p-typetransistor (e.g., the source terminal and a drain terminal).

In some examples, the p-type transistor may act as a switchingcomponent, where the applied voltage is a logical signal that is used toenable conductivity by applying a relatively low logical signal voltage(e.g., a voltage corresponding to a logical “1” state, which may beassociated with a negative logical signal voltage supply), or to disableconductivity by applying a relatively high logical signal voltage (e.g.,a voltage corresponding to a logical “0” state, which may be associatedwith a ground or virtual ground voltage). In various examples where anp-type transistor is employed as a switching component, the voltage of alogical signal applied to the gate terminal may be selected to operatethe transistor at a particular working point (e.g., in a saturationregion or in an active region).

In some examples, the behavior of a p-type transistor may be morecomplex than a logical switching by the gate voltage, and selectiveconductivity across the transistor may also be a function of varyingsource and drain voltages. For example, the applied voltage at the gateterminal may have a particular voltage level that is used to enableconductivity between the source terminal and the drain terminal so longas the source terminal voltage is above a certain level (e.g., above thegate terminal voltage plus the threshold voltage). When the voltage ofthe source terminal voltage falls below the certain level, the p-typetransistor may be deactivated such that the conductive path between thesource terminal and drain terminal is opened.

A transistor of the circuit 200 may be a field-effect transistor (FET),including a metal oxide semiconductor FET, which may be referred to as aMOSFET. These, and other types of transistors may be formed by dopedregions of material on a substrate. In various examples thetransistor(s) may be formed on a substrate that is dedicated to aparticular component of the circuit 200 (e.g., a substrate for the sensecomponent 130 a, a substrate for the amplifier component 280, asubstrate for the memory cell 105-a), or the transistor(s) may be formedon a substrate that is common for particular components of the circuit200 (e.g., a substrate that is common for the sense component 130 a andthe memory cell 105-a). Some FETs may have a metal portion includingaluminum or other metal, but some FETs may implement other non-metalmaterials such as polycrystalline silicon, including those FETs that maybe referred to as a MOSFET. Further, although an oxide portion may beused as a dielectric portion of a FET, other non-oxide materials may beused in a dielectric material in a FET, including those FETs that may bereferred to as a MOSFET.

FIG. 3 illustrates an example of non-linear electrical properties, asdepicted in hysteresis plots 300 a and 300 b, of certain memory cellsthat may be sensed using sense amplifier with lower offset and increasedspeed in accordance with various aspects of the present disclosure. Thehysteresis plots 300 a and 300 b may illustrate an example writingprocess and reading process, respectively, for a memory cell 105employing a ferroelectric capacitor 220 as described with reference toFIG. 2. The hysteresis plots 300-a and 300-b depict the charge, Q,stored on the ferroelectric capacitor 220 as a function of a voltagedifference Vcap, between the terminals of the ferroelectric capacitor220 (e.g., when charge is permitted to flow into or out of theferroelectric capacitor 220 according to the voltage difference Vcap).For example, the voltage difference Vcap may represent the difference involtage between a digit line side of the capacitor 220 and a plate lineside of the capacitor 220 (e.g., Vbottom−Vplate).

A ferroelectric material is characterized by a spontaneous electricpolarization, where the material may maintain a non-zero electric chargein the absence of an electric field. Examples of ferroelectric materialsinclude barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconiumtitanate (PZT), and strontium bismuth tantalate (SBT). Ferroelectriccapacitors 220 described herein may include these or other ferroelectricmaterials. Electric polarization within a ferroelectric capacitor 220results in a net charge at the surface of the ferroelectric material,and attracts opposite charge through the terminals of the ferroelectriccapacitor 220. Thus, charge is stored at the interface of theferroelectric material and the capacitor terminals. Because the electricpolarization may be maintained in the absence of an externally appliedelectric field for relatively long times, even indefinitely, chargeleakage may be significantly decreased as compared with, for example,capacitors without ferroelectric properties such as those used inconventional DRAM arrays. Employing ferroelectric materials may reducethe need to perform refresh operations as described above for some DRAMarchitectures, such that maintaining logic states of an FeRAMarchitecture may be associated with substantially lower powerconsumption than maintaining logic states of a DRAM architecture.

The hysteresis plots 300-a and 300-b may be understood from theperspective of a single terminal of a ferroelectric capacitor 220. Byway of example, if the ferroelectric material has a negativepolarization, positive charge accumulates at the associated terminal ofthe ferroelectric capacitor 220. Likewise, if the ferroelectric materialhas a positive polarization, a negative charge accumulates at theassociated terminal of the ferroelectric capacitor 220.

Additionally, it should be understood that the voltages in thehysteresis plots 300 a and 300 b represent a voltage difference acrossthe capacitor (e.g., between the terminals of the ferroelectriccapacitor 220) and are directional. For example, a positive voltage maybe realized by applying a positive voltage to the perspective terminal(e.g., a cell bottom 222) and maintaining the reference terminal (e.g.,a cell plate 221) at ground or virtual ground (or approximately zerovolts (0V)). In some examples, a negative voltage may be applied bymaintaining the perspective terminal at ground and applying a positivevoltage to the reference terminal (e.g., cell plate 221). In otherwords, positive voltages may be applied to arrive at a negative voltagedifference Vcap across the ferroelectric capacitor 220 and therebynegatively polarize the terminal in question. Similarly, two positivevoltages, two negative voltages, or any combination of positive andnegative voltages may be applied to the appropriate capacitor terminalsto generate the voltage difference Vcap shown in the hysteresis plots300 a and 300 b.

As depicted in the hysteresis plot 300 a, a ferroelectric material usedin a ferroelectric capacitor 220 may maintain a positive or negativepolarization when there is no net voltage difference between theterminals of the ferroelectric capacitor 220. For example, thehysteresis plot 300 a illustrates two possible polarization states, acharge state 305 a and a charge state 310 b, which may represent apositively saturated polarization state and a negatively saturatedpolarization state, respectively. The charge states 305 a and 310 a maybe at a physical condition illustrating remnant polarization (Pr)values, which may refer to the polarization (or charge) that remainsupon removing the external bias (e.g., voltage). The coercive voltage isthe voltage at which the charge (or polarization) is zero. According tothe example of the hysteresis plot 300-a, the charge state 305-a mayrepresent a logic 0 when no voltage difference is applied across theferroelectric capacitor 220, and the charge state 310-a may represent alogic 1 when no voltage difference is applied across the ferroelectriccapacitor 220. In some examples, the logic values of the respectivecharge states may be reversed to accommodate other schemes for operatinga memory cell 105.

A logic 0 or 1 may be written to the memory cell by controlling theelectric polarization of the ferroelectric material, and thus the chargeon the capacitor terminals, by applying a net voltage difference acrossthe ferroelectric capacitor 220. For example, the voltage 315 may be avoltage equal to or greater than a positive saturation voltage, andapplying the voltage 315 across the ferroelectric capacitor 220 mayresult in charge accumulation until the charge state 305-b is reached(e.g., writing a logic 0).

Upon removing the voltage 315 from the ferroelectric capacitor 220(e.g., applying a zero net voltage across the terminals of theferroelectric capacitor 220), the charge state of the ferroelectriccapacitor 220 may follow the path 320 shown between the charge state305-b and the charge state 305-a at zero voltage across the capacitor.Similarly, voltage 325 may be a voltage equal to or lesser than anegative saturation voltage, and applying the voltage 325 across theferroelectric capacitor 220 results in charge accumulation until thecharge state 310-b is reached (e.g., writing a logic 1). Upon removingthe voltage 325 from the ferroelectric capacitor 220 (e.g., applying azero net voltage across the terminals of the ferroelectric capacitor220), the charge state of the ferroelectric capacitor 220 may follow thepath 330 shown between the charge state 310-b and the charge state 310 aat zero voltage across the capacitor. In some examples, the voltage 315and the voltage 325, representing saturation voltages, may have the samemagnitude, but opposite polarity.

To read, or sense, the stored state of a ferroelectric capacitor 220, avoltage may also be applied across the ferroelectric capacitor 220. Inresponse to the applied voltage, the subsequent charge Q stored by theferroelectric capacitor changes, and the degree of the change may dependon the initial polarization state, the applied voltages, intrinsiccapacitance on access lines, and other factors. In other words, thecharge state resulting from a read operation may depend on whether thecharge state 305-a or the charge state 310-a was initially stored, amongother factors.

The hysteresis plot 300-b illustrates an example of reading of storedcharge states 305-a and 310-a. A read voltage 335 may be applied, forexample, as a voltage difference via a digit line 210 and a plate line215 as described with reference to FIG. 2. The hysteresis plot 300-b mayillustrate read operations where the read voltage 335 is negativevoltage difference Vcap (e.g., where Vbottom−Vplate is negative). Anegative read voltage across the capacitor may be referred to as a“plate high” read operation, where a plate line 215 is taken initiallyto a high voltage, and a digit line 210 is initially at a low voltage(e.g., a ground voltage). Although the read voltage 335 is shown as anegative voltage across the ferroelectric capacitor 220, in alternativeoperations a read voltage may be a positive voltage across theferroelectric capacitor 220, which may be referred to as a “plate low”read operation.

The read voltage 335 may be applied across the ferroelectric capacitor220 when a memory cell 105 is selected (e.g., by activating a cellselection component 245 as described with reference to FIG. 2). Uponapplying the read voltage 335 to the ferroelectric capacitor 220, chargemay flow into or out of the ferroelectric capacitor 220 via the digitline 210 and plate line 215, and different charge states may resultdepending on whether the ferroelectric capacitor 220 was at the chargestate 305-a (e.g., a logic 1) or at the charge state 310-a (e.g., alogic 0).

When performing a read operation on a ferroelectric capacitor 220 at thecharge state 310-a (e.g., a logic 0), additional negative charge mayaccumulate across the ferroelectric capacitor 220, and the charge statemay follow path 340 until reaching the charge and voltage of the chargestate 310-c. The amount of charge flowing through the capacitor 220 maybe related to the intrinsic capacitance of the digit line 210 (e.g.,intrinsic capacitance 240 described with reference to FIG. 2).

Accordingly, as shown by the transition between the charge state 310-aand the charge state 310-c, the resulting voltage 350 may be arelatively large negative value due to the relatively large change involtage for the given change in charge. Thus, upon reading a logic 0 ina “plate high” read operation, the digit line voltage, equal to the sumof VPL and the value of (Vbottom−Vplate) at the charge state 310-c, maybe a relatively low voltage. Such a read operation may not change theremnant polarization of the ferroelectric capacitor 220 that stored thecharge state 310 a, and thus after performing the read operation theferroelectric capacitor 220 may return to the charge state 310-a viapath 340 when the read voltage 335 is removed (e.g., by applying a zeronet voltage across the ferroelectric capacitor 220). Thus, performing aread operation with a negative read voltage on a ferroelectric capacitor220 with a charge state 305-a may be considered a non-destructive readprocess.

When performing the read operation on the ferroelectric capacitor 220 atthe charge state 305-a (e.g., a logic 1), the stored charge may reversepolarity as a net negative charge accumulates across the ferroelectriccapacitor 220, and the charge state may follow the path 360 untilreaching the charge and voltage of the charge state 305-c. The amount ofcharge flowing through the capacitor 220 may again be related to theintrinsic capacitance of the digit line 210 (e.g., intrinsic capacitance240 described with reference to FIG. 2). Accordingly, as shown by thetransition between the charge state 305-a and the charge state 305-c,the resulting voltage 355 may be a relatively small negative value dueto the relatively small change in voltage for the given change incharge. Thus, upon reading a logic 1 in a “plate high” read operation,the digit line voltage, equal to the sum of VPL and the value of(Vbottom−Vplate) at the charge state 310-c, may be a relatively highvoltage.

In various examples, a read operation with a negative read voltage(e.g., read voltage 335) may result in a reduction or a reversal ofremnant polarization of the capacitor 220 that stored the charge state305 a. In other words, according to the properties of the ferroelectricmaterial, after performing the read operation the ferroelectriccapacitor 220 may not return to the charge state 305 a when the readvoltage 335 is removed (e.g., by applying a zero net voltage across thecapacitor 220). Rather, when applying a zero net voltage across theferroelectric capacitor 220 after a read operation with read voltage335, the charge state may follow path 365 from the charge state 305 c tothe charge state 305 d, illustrating a net reduction in polarizationmagnitude (e.g., a less positively polarized charge state than initialcharge state 305 a). Thus, performing a read operation with a negativeread voltage on a ferroelectric capacitor 220 with a charge state 305-amay be a destructive read process. However, in some sensing schemes, areduced remnant polarization may still be read as the same stored logicstate as a saturated remnant polarization state (e.g., supportingdetection of a logic 1 from both the charge state 305-a and the chargestate 305-d), thereby providing a degree of non-volatility for a memorycell 105 with respect to read operations.

The transition from the charge state 305-a to the charge state 305-d maybe illustrative of a sensing operation that is associated with a partialreduction and/or partial reversal in polarization of a ferroelectriccapacitor 220 of a memory cell 105 (e.g., a reduction in the magnitudeof charge Q from the charge state 305-a to the charge state 305-d). Invarious examples, the amount of change in polarization of aferroelectric capacitor 220 of a memory cell 105—as a result of asensing operation may be selected according to a particular sensingscheme. In some examples, sensing operations having a greater change inpolarization of a ferroelectric capacitor 220 of a memory cell 105 maybe associated with relatively greater robustness in detecting a logicstate of a memory cell 105. In some sensing schemes, sensing a logic 0of a ferroelectric capacitor 220 at the charge state 305 a may result ina full reversal of polarization, with the ferroelectric capacitor 220transitioning from the charge state 305-a to the charge state 310-aafter the sensing operation.

The position of the charge state 305-c and the charge state 310-c afterinitiating a read operation may depend on a number of factors, includingthe specific sensing scheme and circuitry. In some cases, the finalcharge may depend on the net capacitance of the digit line 210 coupledwith the memory cell 105, which may include an intrinsic capacitance240, amplifier capacitors, and others. For example, if a ferroelectriccapacitor 220 is electrically coupled with digit line 210 at 0V and theread voltage 335 is applied to the plate line, the voltage of the digitline 210 may rise when the memory cell 105 is selected due to chargeflowing from the ferroelectric capacitor 220 to the net capacitance ofthe digit line 210. Thus, a voltage measured at a sense component 130may not be equal to the read voltage 335, or the resulting voltages 350or 355, and instead may depend on the voltage of the digit line 210following a period of charge sharing.

The position of the charge state 305-c and the charge state 310-c onhysteresis plot 300-b upon initiating a read operation may depend on thenet capacitance of the digit line 210 and may be determined through aload-line analysis. In other words, the charge states 305-c and 310-cmay be defined with respect to the net capacitance of the digit line210. As a result, the voltage of the ferroelectric capacitor 220 afterinitiating a read operation (e.g., voltage 350 when reading theferroelectric capacitor 220 that stored the charge state 310-a, voltage355 when reading the ferroelectric capacitor 220 that stored the chargestate 305-a), may be different and may depend on the initial state ofthe ferroelectric capacitor 220.

The initial state of the ferroelectric capacitor 220 may be determinedby comparing the voltage of a digit line 210 (or a related voltage, suchas the voltage across an amplifier capacitor) resulting from the readoperation with a reference voltage (e.g., via a reference line 255 asdescribed with reference to FIG. 2, or via a common access line). Insome examples, the digit line voltage may be the sum of the plate linevoltage and the final voltage across the ferroelectric capacitor 220(e.g., voltage 350 when reading the ferroelectric capacitor 220 having astored the charge state 310-a, or voltage 355 when reading theferroelectric capacitor 220 having a stored the charge state 305-a). Insome examples, the digit line voltage may be the difference between theread voltage 335 and the final voltage across the capacitor 220 (e.g.,(read voltage 335−voltage 350) when reading the ferroelectric capacitor220 having a stored the charge state 310-a, (read voltage 335−voltage355) when reading the ferroelectric capacitor 220 having a stored thecharge state 305-a).

In some sensing schemes, a reference voltage may be generated such thatthe reference voltage is between the possible voltages that may resultfrom reading different logic states. For example, a reference voltagemay be selected to be lower than the resulting digit line voltage whenreading a logic 1, and higher than the resulting digit line voltage whenreading a logic 0. In other examples, a comparison may be made at aportion of a sense component 130 that is different from a portion wherea digit line is coupled, and therefore a reference voltage may beselected to be lower than the resulting voltage at the comparisonportion of the sense component 130 when reading a logic 1, and higherthan the resulting voltage at the comparison portion of the sensecomponent 130 when reading a logic 0. During comparison by the sensecomponent 130, the voltage based on the sensing may be determined to behigher or lower than the reference voltage, and the stored logic stateof the memory cell 105 (e.g., a logic 0, a logic 1) may thus bedetermined.

During a sensing operation, the resulting signals from reading variousmemory cells 105 may be a function of manufacturing or operationalvariations between the various memory cells 105. For example, capacitorsof various memory cells 105 may have different levels of capacitance orsaturation polarization, so that a logic 1 may be associated withdifferent levels of charge from one memory cell to the next, and a logic0 may be associated with different levels of charge from one memory cellto the next. Further, intrinsic capacitance (e.g., intrinsic capacitance240 described with reference to FIG. 2) may vary from one digit line 210to the next digit line 210 in a memory device, and may also vary withina digit line 210 from the perspective of one memory cell 105 to the nextmemory cell 105 on the same digit line. Thus, for these and otherreasons, reading a logic 1 may be associated with different levels ofdigit line voltage from one memory cell to the next (e.g., resultingvoltage 350 may vary from reading one memory cell 105 to the next), andreading a logic 0 may be associated with different levels of digit linevoltage from one memory cell to the next (e.g., resulting voltage 355may vary from reading one memory cell 105 to the next).

In some examples, a reference voltage may be provided between astatistical average of voltages associated with reading a logic 1 and astatistical average of voltages associated with reading a logic 0, butthe reference voltage may be relatively closer to the resulting voltageof reading one of the logic states for any given memory cell 105. Theminimum difference between a resulting voltage of reading a particularlogic state (e.g., as a statistical value for reading a plurality ofmemory cells 105 of a memory device) and an associated level of areference voltage may be referred to as a “minimum read voltagedifference,” and having a low minimum read voltage difference may beassociated with difficulties in reliably sensing the logic states ofmemory cells in a given memory device.

To reliably detect the logic state of a plurality of memory cells 105that are subject to manufacturing and operational variations, a sensecomponent 130 may be designed to employ self-referencing techniques,where a memory cell 105 itself is involved in providing a referencesignal when reading the memory cell 105. However, when using the samememory cell 105 for providing both a sense signal and a referencesignal, the sense signal and the reference signal may be substantiallyidentical when performing access operations that do not change a statestored by the memory cell 105. For example, when performing aself-referencing read operation on a memory cell 105 storing a logic 1(e.g., storing a charge state 310 a), a first access operation that mayinclude applying the read voltage 335 may follow path 340, and a secondoperation that may also include applying the read voltage 335 may alsofollow path 340, and the first and second access operations may resultin substantially the same access signals (e.g., from the perspective ofthe memory cell 105). In such cases, when employing a sense component130 that relies on a difference between a sense signal and a referencesignal to detect a logic state stored by the memory cell 105, some otherportion of a memory device may provide such a difference in the eventthat access operations might provide substantially equal sense andreference signals.

FIG. 4 illustrates an example of a circuit 400 that supports senseamplifiers with lower offset and higher speed for sensing memory cellsin accordance with various examples of the present disclosure. Thecircuit 400 may include a memory cell 105-b, a sense amplifier 225-a(e.g., in a sense component 130) for sensing a logic state of the memorycell 105-b, and optional latch circuit 430 for storing a sensed logicstate of memory cell 105-b. The memory cell 105-b and the senseamplifier 225-a may be examples of the respective components describedwith reference to FIGS. 1 and 2.

The circuit 400 may include a word line 205-a, a digit line 210-a, and aplate line 215-a. Each of the word line 205-a, the digit line 210-a, andthe plate line 215-a may be coupled with one or more memory cells 105,including the memory cell 105-b as shown. The digit line 210-a and theplate line 215-a may be associated with voltages V_(DL) and V_(PL),respectively, as shown. The circuit 400 may include the word line 205-afor selecting or deselecting the memory cell 105-b (e.g., by way oflogic signal WL). The circuit 400 may include the plate line 215-a foraccessing a cell plate of a capacitor 220-a of the memory cell 105-b.Thus, the memory cell 105-b may represent a memory cell coupled with orbetween a first access line (e.g., the digit line 210-a) and a secondaccess line (e.g., the word line 205-a).

Sense amplifier 225-a may include amplifier component 410 and amplifiercapacitor 415. Sense amplifier 225-a may further include switchingcomponents 260-d, 260-e, 260-f for selectively coupling various nodes ofamplifier component 410 and amplifier capacitor 415 with, for example,digit line 210-a, I/O line 265-a, and/or other nodes of amplifiercomponent 410 and amplifier capacitor 415. Circuit 400 may include oneor more additional switching components (e.g., switching components260-a, 260-b, 260-c, 260-g) for coupling and uncoupling amplifiercomponent 410 and/or digit line 210-a with various voltage sources 235.

Amplifier component 410 may have a first input 435, a second input 440,a first output 455, and a second output 460. In some cases, the firstinput 435 may be referred to as a positive input. In some cases, thesecond input 440 may be referred to as a negative input or feedbackinput. First output 455 may be an inverse of second output 460; that is,a voltage or current that is output by amplifier component 410 at secondoutput 460 may be the opposite polarity of a voltage or current that isoutput by amplifier component at first output 455.

The circuit 400 may include a variety of voltage sources 235, which maybe coupled with various voltage supplies and/or common grounding orvirtual grounding points of a memory device that may include the examplecircuit 400.

A voltage source 235-g may represent an amplifier component 410 highvoltage source, and may be associated with a voltage V4. A voltagesource 235-h may represent an amplifier component 410 low voltage sourceor supply voltage, and may be associated with a voltage V5. The voltagesource 235-g may be coupled with a first supply node of the amplifiercomponent 410. The voltage source 235-h may be selectively coupled witha second supply node of the amplifier component 410 via a switchingcomponent 260-f.

In some examples, the amplifier component 410 may be supplied with apositive voltage and a negative voltage via the voltage sources 235-gand 235-h. As one example, V4 may be selected to be equal to 1.0V and V5may be selected to be equal to −0.5V. In some cases, amplifier component410 may be coupled with one or more additional voltage supplies (notshown).

The first and second inputs 435, 440 of amplifier component 410 may beselectively coupled with one or more voltage sources 235-d, 235-e, 235-fvia switching components 260-a, 260-b, and 260-c, respectively.

In some cases, voltage source 235-d may be associated with voltage V1,which may be a sense voltage V_(SENSE). In some cases, voltage source235-e may be associated with voltage V2, which may be a referencevoltage V_(REF). In some cases, voltage source 235-f may be associatedwith voltage V3, which may be a pre-charge voltage V_(PRE). In somecases, the pre-charge voltage may be the same as the sense voltage. Insome cases, one or more of voltage sources 235-d, 235-e, 235-f areselectable voltage sources such that a single voltage source may takethe place of two or more of voltage sources 235-d, 235-e, 235-f.

In some examples, the sense amplifier 225-a may be in electroniccommunication with a memory controller (not shown), such as a memorycontroller 150 described with reference to FIG. 1, which may controlvarious operations of the sense amplifier 225-a and/or of amplifiercomponent 410.

In some examples, the amplifier component 410 may be configurable (e.g.,via activating or deactivating various switching components (not shown)inside amplifier component 410) to operate in an amplifier mode. As oneexample, when amplifier component 410 is configured to operate in anamplifier mode, a voltage or current at the first output 455 and secondoutput 460 of the amplifier component may be proportional to adifference in voltage or current between the first input 435 and thesecond input 440 of the amplifier component.

In some examples, the amplifier component 410 may be configurable (e.g.,via activating or deactivating various switching components inside theamplifier component 410) to operate in a latch mode. As one example,when amplifier component 410 is configured to operate in a latch modeand amplifier component 410 is activated, amplifier component 410 maydetermine a state of the memory cell and latch the state. In someexamples, amplifier component 410 may latch the state by outputting thestate to a latch circuit 430 (e.g., a latch circuit exterior to theamplifier component 410), which may store the state and subsequentlyoutput the state to one or more other components. In some examples, theamplifier component 410 may latch the state by storing the state usingtransistors (not shown) within amplifier component 410 itself, and maysubsequently output the state (e.g., via I/O line 265-a) to othercomponents or circuits. In other words, in some cases, amplifiercomponent 410 may be configurable to perform functions similar to aseparate latch circuit 430, thereby eliminating the need for latchcircuit 430.

In the example of circuit 400, sense amplifier 225-a includes anamplifier capacitor 415, which may have a first node 420 associated witha voltage of V_(AMPCAP) and a second node 425 that is coupled with digitline 210-a via selection component 245-b. In some examples, second node425 of amplifier capacitor 415 may, during portions of a read operation,reach a voltage that is essentially the same as V_(DL).

In the example of circuit 400, the sense amplifier 225-a may include aswitching component 260-e that may be used to selectively couple ordecouple the second output 460 of the amplifier component 410 with thefirst node 420 of the amplifier capacitor 415 (e.g., by activating ordeactivating switching component 260-e). In this case, the senseamplifier 225-a illustrates an example of including an amplifiercomponent 410 with a capacitive feedback line (e.g., via the capacitanceof the amplifier capacitor 415) that may be selectively enabled ordisabled (e.g., by activating or deactivating switching component260-e).

In the example of circuit 400, sense amplifier 225-a includes aswitching component 260-f, which may be used to selectively couple ordecouple the second output 460 of amplifier component 410 with thesecond input 440 of amplifier component 410 (e.g., by activating ordeactivating switching component 260-f). In other words, sense amplifier225-a may include an amplifier component 410 having a direct feedbackline that may be selectively enabled or disabled (e.g., via theswitching component 260-f).

The circuit 400 may include other switching components or selectioncomponents to selectively couple or uncouple amplifier component 410and/or amplifier capacitor 425 with access lines 210 for various accessoperations. For example, the circuit 400 may include a selectioncomponent 260-d to support selectively coupling or uncoupling the memorycell 105-b with amplifier component 410 (e.g., via digit line 210-a)and/or with amplifier capacitor 415. Circuit 400 includes digit lineselection component 245-b that may be used for coupling and uncouplingdigit line 210-a with sense amplifier 225-a.

The amplifier component 410 and/or optional latch circuit 430 may, insome examples, be used to latch signals associated with a read operationwhen detecting a logic state stored by a memory cell 105-b. Electricalsignals associated with such latching may be communicated between thesense amplifier 225-a, optional latch circuit 430, and/or anotherinput/output component 140 (not shown), for example, via I/O line 265-a.In some examples, the sense amplifier 225-a may be in electroniccommunication with a memory controller (not shown), such as a memorycontroller 150 described with reference to FIG. 1, which may controlvarious operations of the sense amplifier 225-a.

Although the sense amplifier 225-a, amplifier component 410, latchcircuit 430, switching components 260, selection component 260, andvoltage sources 235 are illustrated with respective dashed lines asreflecting particular boundaries, such boundaries are shown forillustrative purposes only. In other words, any one or more of anamplifier component 410, latch circuit 430, switching components 260, orvoltage sources 235 in accordance with the present disclosure may haveboundaries different than the dashed boundaries shown in the circuit400. For example, a sense amplifier 225-a or an amplifier component 410may or may not include voltage sources or other voltage supplies, suchthat the voltage sources or voltage supplies may be within theillustrative boundaries or outside the illustrative boundaries.

Each of the components illustrated in circuit 400 (e.g., sense amplifier225-a, switching components 260, selection components 245, amplifiercomponent 410, latch circuit 430, voltage sources 235) may be controlledusing signals provided by a memory controller (not shown), such as amemory controller 150 described with reference to FIG. 1. In someexamples, certain logical signals, such as logical signal WL, may beprovided by a memory controller or by other components. For example,logical signal WL may be provided by a row decoder (not shown), such asa row decoder 125 described with reference to FIG. 1.

FIG. 5 illustrates an example of a circuit 500 that supports senseamplifiers with lower offsets and higher speeds for sensing memory cellsin accordance with various examples of the present disclosure. Circuit500 provides additional details with respect to the circuitry of aconfigurable amplifier component, such as amplifier component 410described with respect to FIG. 4. Circuit 500 may depict an example ofan amplifier component that is configurable to operate in an amplifiermode or in a latch mode. Circuit 500 may depict an example of anamplifier that is configurable to operate, in the latch mode, as a latch(e.g., a half latch).

Circuit 500 includes exemplary amplifier component 410-a. Amplifiercomponent 410-a includes internal transistors 505 and internal switchingcomponents 510. In some examples, switching components 510 may includeswitching transistors, such as PMOS, NMOS, or CMOS switchingtransistors. In some cases, activating a switching component 510includes supplying an activation signal to the switching component, suchas applying an activation voltage to a gate of a switching transistor.

In some examples, transistors 505 may be MOS transistors. In some cases,transistors 505-a and 505-c may be PMOS transistors, and transistors505-b and 505-d may be NMOS transistors. Other examples of amplifiercomponent 410 may use other types of transistors.

Amplifier component 410-a is directly coupled with voltage source 235-i,and coupled with voltage source 235-j via switching component 260-h andselection component 245-c. In some examples, voltage source 235-i isassociated with voltage V6, which may be a high voltage (e.g., V_(HSA)).In some examples, voltage source 235-j is associated with voltage V7,which may be a low voltage or supply voltage (e.g., V_(SS)). As depictedin FIG. 4, amplifier component may additionally be coupled with otherhigh and low voltage supplies (e.g., 235-g, 235-h). Amplifier component410-a may be activated by activating switching component 260-h andsupply voltage selection component 245-c to couple amplifier component410-a with voltage V7 (e.g., V_(SS)).

Amplifier component includes a first input 435-a, a second input 440-a,a first output 455-a, and a second output 460-a. In some examples, firstinput 435-a may be referred to as a positive input, and second input440-a may be referred to as a negative input or feedback input.

Switching components 510 in amplifier component 410-a may be used tocouple or uncouple various nodes of transistors 505 with each otherand/or with inputs or outputs of amplifier component. For example,activating switching component 510-d may couple the gate of transistor505-a with first output 455-a. Similarly, activating switching component510-c may couple the gate of transistor 505-a with the gate oftransistor 505-c, which may be a configuration used to implement acurrent mirror functionality. Conversely, deactivating switchingcomponent 510-c may uncouple the gate of transistor 505-a from the gateof transistor 505-c. Activating switches 510-e and 510-f cross-couplestransistors 505-a and 505-c. This configuration may be used to implementa latch functionality.

Amplifier component 410-a may be configurable to operate in differentmodes (e.g., amplifier mode, latch mode) during different portions of aread operation of a memory cell by activating or deactivating variousswitching components 510. The operation of circuit 500 having amplifiercomponent 410-a, including its operation while amplifier component 410-ais configured to operate in an amplifier mode or in a latch mode, isdescribed in more detail with respect to FIGS. 6-11.

FIG. 6 illustrates an example of a circuit 600 that supports senseamplifiers with lower offsets and higher speeds for sensing memory cellsin accordance with various examples of the present disclosure. Circuit600 includes amplifier component 410-a, memory cell 105-b, senseamplifier 225-a, voltage sources 235, switching components 260,selection components 245, and optional latch circuit 430, as describedwith respect to FIGS. 4-5. Circuit 600 may be an example of aconfiguration of circuits 400 and 500 during a portion of a readoperation.

In some cases, a read operation of a memory cell includes a pre-chargingoperation for pre-charging digit line 210-a to a voltage (e.g., a sensevoltage) before coupling memory cell 105-a with digit line 210-a toenable more accurate sensing of the logic state of memory cell 105-a.

In some examples, a pre-charging operation may include a firstpre-charging portion. During the first pre-charging portion, digit line210-a may be pre-charged to a first voltage by activating switchingcomponents 260-c and 260-d along with digit line selection component245-b to couple voltage source 235-f associated with voltage V3 (e.g.,V_(PRE)) with digit line 210-a. The voltage of digit line 210-a may, insome examples, approach or reach voltage V3 during the firstpre-charging portion.

In some cases, amplifier component 410-a may not be used during thefirst pre-charging portion of the read operation. Thus, in some cases,amplifier component 410-a may not be activated during the firstpre-charging portion of the read operation because switching component260-h may be deactivated and amplifier component 410-a may be uncoupledfrom voltage source 235-j (e.g., voltage supply V_(SS)). Internalswitches 510-a and 510-b may be activated, and remaining internalswitches 510-c, 510-d, 510-e, and 510-f may be deactivated.

FIG. 7 illustrates an example of a circuit 700 that supports senseamplifiers with lower offsets and higher speeds for sensing memory cellsin accordance with various examples of the present disclosure. Circuit700 may be an example of a configuration of circuits 400 and 500 duringa portion of a read operation.

As noted with respect to FIG. 6, in some cases, a read operation of amemory cell includes a pre-charging operation to pre-charge digit line210-a to a sense voltage before coupling memory cell 105-a with digitline 210-a to enable more accurate sensing of the logic state of memorycell 105-a. Circuit 700 may be an example of circuits 400 and 500 asconfigured for operation during a second pre-charging portion of a readoperation of a memory cell. In some cases, the second pre-chargingportion may follow the first pre-charging portion described with respectto FIG. 6. In some cases, a memory device may perform the secondpre-charging portion without performing the first pre-charging portion,or may perform the first pre-charging portion without performing thesecond pre-charging portion.

During the second pre-charging portion, the voltage of digit line 210-amay be changed from a first voltage (e.g., approximately V_(PRE)) to asecond voltage, which may be referred to as an offset-adjusted sensevoltage V_(SENSEOFF).

In the example depicted in FIG. 7, amplifier component 410-a may beconfigured to operate in an amplifier mode by activating switchingcomponents 510-d and 510-c, and deactivating switching components 510-eand 510-f In this configuration, transistors 505-a and 505-b may beconfigured to operate as a current mirror. Amplifier component 410-a maybe activated by activating switching component 260-h and voltage supplyselection component 245-c, thereby coupling amplifier component 410-awith voltage source 235-h, which may be a voltage supply (e.g., V_(SS)).Amplifier component 410-a may be uncoupled from voltage source 235-g bydeactivating switching components 510-a, 510-b.

During the second pre-charging portion of the read operation, voltagesource 235-d is coupled with first input 435-a of amplifier component410-a by activating switching component 260-a, and a feedback path maybe enabled from the second output 460-a and the second input 440-a ofamplifier component 410-a by activating switching components 260-e and260-f. In addition, digit line 210-a may be coupled with second input440-a of amplifier component 410-a. Voltage source 235-d is associatedwith voltage V1, which may be a sense voltage (e.g., V_(SENSE)). In someexamples, voltage V1 may be the same as voltage V3 (e.g., the pre-chargevoltage and the sense voltage may be the same voltage). In otherexamples, voltage V1 may be different than (e.g., higher than, lowerthan) voltage V3.

During the second pre-charging portion of the read operation, whileamplifier component 410-a may be configured in the amplifier mode,amplifier component 410-a may be used as a voltage buffer to adjust thevoltage of digit line 210-a from a first voltage (e.g., the voltage towhich the digit line was pre-charged in the first pre-charging portion,or another voltage) to a second voltage (e.g., V_(SENSEOFF)). The secondvoltage may be based on a difference between the voltage at the firstinput 435-a (e.g., V_(INPUT1), which may be V_(SENSE) during thisportion) and the second input 440-a (e.g., V_(INPUT2), which may beV_(DL) during this portion), and may include the effect of a voltageoffset of amplifier component 410-a. (Such a voltage offset may be aresult of mismatched transistors in amplifier component 410-a due toprocess variations.) That is, using amplifier component 410-a to adjustthe voltage of digit line 210-b from the first voltage to the secondvoltage during the second pre-charging portion may cause digit line210-b to be pre-charged to an offset-adjusted voltage that may accountfor the effect of the voltage offset of amplifier component 410-a.

The above-described pre-charging process, as performed during the firstpre-charging portion and/or the second pre-charging portion, may haveseveral benefits in the context of sensing a memory cell. Among others,using a voltage source 235-d to pre-charge the digit line during thefirst pre-charging portion may allow the digit line 210-b to be quicklycharged to a voltage that is close to the sense voltage and may reducethe DC current constraint on the amplifier component (as compared withperforming the entire pre-charging process using the amplifiercomponent, for example).

In addition, using the amplifier component in the second pre-chargingportion to pre-charge the digit line to an offset-adjusted sense voltagemay enable faster latching when the amplifier component is also used foramplifying the signal received from the memory cell and latching thestate, as will be described in more detail with respect to FIGS. 8-10.

FIG. 8 illustrates an example of a circuit 800 that supports senseamplifiers with lower offsets and higher speeds for sensing memory cellsin accordance with various examples of the present disclosure. Circuit800 may be an example of a configuration of circuits 400 and 500 duringa portion of a read operation.

In some cases, a read operation of a memory cell may include a signaldevelopment portion during which the memory cell (e.g., memory cell 105)is coupled with the digit line and is discharging its charge (e.g., froma ferroelectric capacitor 220) onto the digit line, thereby potentiallychanging the amount of charge on the digit line and/or the voltage ofthe digit line.

As depicted in FIG. 8, amplifier component 410-a may include amplifiercapacitor 415 having a first node 420 and a second node 425. In somecases, during the signal development portion of the read operation, thefirst node 420 of amplifier capacitor 415 may be coupled with the secondoutput 460-a of amplifier component by activating switching component260-e. The second node 425 of amplifier capacitor 415 may be coupledwith the digit line 210-a via activated selection component 245-b. Thefirst input 435-a of amplifier component 410-a may be coupled withvoltage source 235-d by activating switching component 260-a anddeactivating switching component 260-b. Thus, the first input 435-a maybe set to a sense voltage V_(SENSE), while the second input 440-a may beset to the voltage of digit line 210-a (e.g., V_(DL)) by activatingswitching component 260-d.

During the signal development portion, the amplifier component 410-a maybe configured to operate in an amplifier mode and may amplify adifference between the sense voltage V_(SENSE) and the voltage of thedigit line 210-a. A second output 460-a of the amplifier component 410-amay be coupled with the amplifier capacitor 415.

In some cases, during the signal development portion of the operation,amplifier component 410-a may be configured to operate in the amplifiermode by activating switching components 510-c and 510-d to configuretransistors 505-a and 505-c to operate as a current mirror, anddeactivating switching components 510-a, 510-b, 510-e, and 510-f. Duringthe signal development portion, feedback from the second output 460-a tothe second input 440-a of amplifier component 410-a may be disabled bydeactivating switching component 260-f to uncouple second input 440-afrom second output 460-a.

In the configuration depicted in FIG. 8, the amplifier component 410-aand the amplifier capacitor 415 may function together as a currentintegrator to integrate the charge received from the memory cell duringthe signal development portion of the read operation such that thevoltage across the amplifier capacitor 415 changes based on (e.g., inproportion to) the amount of charge transferred between the memory celland the amplifier capacitor (via the digit line). The voltage across theamplifier capacitor may therefore be used to determine the logic stateof memory cell 105-a during a portion (e.g., a subsequent latch portion)of the read operation, as described below with respect to FIGS. 9-10.

The voltage of the digit line may remain at or near the offset-adjustedsense voltage V_(SENSEOFF) as the charge is transferred between memorycell 105-b and the amplifier capacitor 415 and integrated. At the end ofthe signal development portion of the read operation, the amplifiercapacitor 415 may store an amount of charge that is based on the amountof charge discharged from the memory cell, which is in turn based on thelogic state of the memory cell. Thus, the voltage across amplifiercapacitor 415 (e.g., the voltage at the first node 420) at the end ofthe signal development portion may be used to determine the logic stateof the memory cell.

In some examples, during the signal development portion of the readoperation, a DC current of the amplifier component may be bigger thanthe memory cell current. For example, the memory cell current for aswitching memory cell (e.g., for a memory cell during the signaldevelopment portion) may be approximately 1 μA. In this case, a DCcurrent for the amplifier component with an approximately 2 μA bias maybe appropriate.

In some examples, the above-described techniques for reading a memorycell using a sense amplifier having a lower offset and higher speed,such as sense amplifier 225-a having amplifier component 410-a, mayenable faster signal development relative to some cascode-based senseschemes or other types of sensing schemes, thereby increasing the speedof the read operation. Signal development may be faster because thevoltage of digit line 210-a may be more stable than in a cascode-basedimplementation, and/or because the polarization of memory cell 105-a(e.g., the polarization described with respect to FIG. 3) may occur morequickly because the amplifier component is capable of maintaining ahigher bias across the memory cell during the signal development portionof the read operation.

FIG. 9 illustrates an example of a circuit 900 that supports senseamplifiers with lower offsets and higher speeds for sensing memory cellsin accordance with various examples of the present disclosure. Circuit900 may be an example of a configuration of circuits 400 and 500 duringa portion of a read operation.

In some cases, a read operation of a memory cell includes latching astate of a memory cell 105-a by performing a latch operation after thesignal development portion of the read operation. A latch operation mayinclude determining the state (e.g., by comparing the voltage of digitline 210-a and/or the voltage at the first node 420 of amplifiercapacitor 415 with a reference voltage) and storing the state. In someexamples, an amplifier component 410 may be configurable to operate in alatch mode such that activating the amplifier component while it isconfigured in the latch mode may cause the amplifier component todetermine the state and store the state internally (e.g., for subsequentoutput to external components), or to output the state to a separatelatch circuit that stores the state, or some combination.

Circuit 900 may be an example of circuits 400 and 500 as configured toprepare for a latch operation. To prepare for the latch operation,amplifier component 410-a may be configured to operate in a latch modeby activating switching components 510-e and 510-f to configuretransistors 505-a, 505-c as a latch circuit (e.g., a half-latch circuit)by cross-coupling the transistors, and deactivating switching components510-c and 510-d to deactivate the current mirror. Switching components510-a and 510-b may be activated to couple amplifier component withvoltage source 235-g (e.g., V_(HSA)).

Preparing for the latch operation may also include decoupling the secondinput 440-a of amplifier component 410-a from digit line 210-a bydeactivating switching component 260-d and coupling second input 440-awith the first node 420 of amplifier capacitor 415 by activatingswitching component 260-f The first input 435-a of amplifier component410-a may be coupled with voltage source 235-e, which is associated withvoltage V2 (e.g., a reference voltage, V_(REF)). Thus, in theconfiguration depicted in FIG. 9, amplifier component 410-a may beconfigured to determine, when it is activated in the latch mode, a logicstate of memory cell 105-a by comparing a voltage of the first node 420of amplifier capacitor 415 with a reference voltage V_(REF).

In some examples, to prepare for the latch operation, amplifiercomponent 410-a may be turned off or inactivated by deactivatingswitching component 260-h to decouple amplifier component 410-a fromvoltage supply 235-h (e.g., V_(SS)); that is, in some cases, amplifiercomponent 410-a may not perform a latch operation until it is activated(e.g., fired) by coupling it with voltage supply 235-h while it isconfigured in the latch mode.

FIG. 10 illustrates an example of a circuit 1000 that supports senseamplifiers with lower offsets and higher speeds for sensing memory cellsin accordance with various examples of the present disclosure. Circuit1000 may be an example of a configuration of circuits 400 and 500 duringa portion of a read operation.

After preparing for the latch operation as described above with respectto FIG. 9, amplifier component 410-a may be activated (e.g., fired)while it is configured in the latch mode to latch the state of memorycell 105-a. Amplifier 410-a may be activated by activating switchingcomponent 260-h to couple amplifier component 410-a with voltage source235-h (e.g., V_(SS)) and deactivating switching components 510-a, 510-bto decouple the gates of transistors 505-a, 505-c from voltage source235-g (e.g., V_(HSA)). In some cases, amplifier component 410-a may beactivated in response to a trigger condition being met (e.g., based on alatch trip point).

In some cases, activating amplifier component 410-a while it isconfigured in the latch mode may cause amplifier component 410-a todetermine a logic state of memory cell 105-a by comparing the voltage ofthe first node 420 of amplifier capacitor 415 with a reference voltageV_(REF) received from voltage source 235-e (e.g., as described withrespect to FIG. 2). In some cases, amplifier component 410-a maydetermine the state as either a first state or a second state (e.g., asa “0” or a “1”).

In some cases, activating amplifier component 410-a while it isconfigured in the latch mode may cause amplifier component 410-a tostore the determined state using transistors inside amplifier component410-a (e.g., using transistors 505-a and 505-c as an internal latchcircuit).

In some cases, amplifier component 410-a may be configurable, in latchmode, to operate as a half latch circuit that is capable of storing onestate and providing the other state to a separate latch circuit 430. Insome cases, activating amplifier component while it is configured in thelatch mode may cause amplifier component 410-a to output the state to anexternal component (e.g., to a latch circuit 430 if a latch circuit isused to store the state) or to another component (e.g., if the amplifiercomponent 410-a stores the state).

In some cases, an amplifier component 410 may use some of the sameinternal circuitry (e.g., transistors 505, switching components 510)when it is operating in amplifier mode (e.g., when it is used forpre-charging the digit line during the second pre-charging portionand/or amplifying a signal during the signal development portion) andwhen it is operating in a latch mode (e.g., when it is used fordetermining a state and/or storing the state). By re-using circuitry inamplifier component 410 for different operations, a trigger condition(e.g., the latch trip point) for activating the amplifier component410-a in the latch mode may track the variation of the signal receivedfrom the memory cell during signal development better than alternatives,such as a cascode-based implementation, because the offset introduced byamplifier component 410 into the signal received from the memory cellmay be essentially cancelled out by including the same offset in thesense voltage (e.g., V_(SENSEOFFSET)) of the second pre-chargingportion. In this case, amplifier component 410-a may be able to latchthe state more quickly, thereby improving the performance of the memorydevice 100.

FIG. 11 shows a timing diagram 1100 illustrating operations of anexample read operation that supports sense amplifiers with lower offsetand higher speed for sensing memory cells in accordance with variousexamples of the present disclosure. The timing diagram 1100 is describedwith reference to components of the example circuits 400, 500, 600, 700,800, 900, and 1000 of FIGS. 4-10, but may be illustrative of operationsthat may be performed with different circuit arrangements as well.Voltages and time ranges depicted in timing diagram 1100 may beapproximate and are not to scale; they are intended to illustrategeneral circuit behavior rather than specific timing and voltagecharacteristics.

In the example of timing diagram 1100, memory cell 105-b may initiallystore a logic state (e.g., a logic 0 state, a logic 1 state) asdescribed herein (e.g., with reference to FIG. 3). Certain signalsillustrated in the timing diagram 1100 are therefore shown asalternatives associated with reading the different logic states, asindicated by the notation state=1 or state=0 (e.g., as associated withthe respective logic states) where such signals are different.

In some examples, the read operation illustrated by timing diagram 1100may begin at t0 with an initial state in which the word line is notasserted (e.g., logical signal WL is deactivated by setting it to V₀),and the digit line 210-a is isolated from voltage source 235-f (e.g.,pre-charge voltage V3) by deactivating switching component 260-c, 260-d,and/or deactivating digit line selection component 245-b.

At time t1, a first portion (e.g., a first pre-charging portion) of theread operation may begin, as described with respect to FIG. 6. Duringthe first portion, amplifier component 410-a may be inactive (e.g.,switching component 260-h and/or voltage supply selection componenttransistor 245-c may be deactivated). Amplifier component 410-a may beconfigured with some or all of internal switching components 510deactivated.

The first portion may include activating switching components 260-c and260-d and voltage supply selection component 245-c to couple digit line210-a with voltage source 235-f, which may be associated with voltage V3(e.g., a pre-charge voltage, V_(PRE)). Activating switching components260-c and 260-d and selection component 245-b may also couple digit line210-a and voltage source 235-f with the second input 440-a of amplifiercomponent 410-a and the second node 425 of amplifier capacitor 415.

During the first pre-charging portion, the voltage of the digit line,V_(DL) 1105, may begin to rise to a first voltage (e.g., towardsV_(PRE)). The voltage at the second node of amplifier capacitor 415V_(AMPCAP) 1115, the voltage at the second input 440 of amplifiercomponent 410-a V_(INPUT2) 1125, and the voltage at the second output460 of amplifier component 410-a V_(OUTPUT) 1130 may also increase(e.g., begin to rise).

At time t2, a second portion (e.g., a second pre-charging portion) ofthe read operation may begin, as described with respect to FIG. 7.

The second portion may include deactivating switching component 260-c touncouple digit line 210-a from voltage source 235-f, and activatingswitching component 260-a to couple voltage source 235-d with the firstinput 435-a of amplifier component 410-a. Voltage source 235-d may beassociated with voltage V1 (e.g., a sense voltage, V_(SENSE)). Thesecond portion may also include activating switching components 260-eand 260-f to couple the second output 460-a of amplifier component 410-awith the second input 440-a of amplifier component 410-a (e.g., toenable a feedback line).

Activating switching components 260-d and 260-f may also, in someexamples, couple digit line 210-a with the second input 440-a ofamplifier component 410-a.

During the second portion, amplifier component 410-a may be configuredto operate in an amplifier mode. In some cases, this may be based onactivating switching components 510-c and 510-d and deactivatingswitching components 510-a, 510-b, 510-e, and 510-f. In thisconfiguration, the gate of transistor 505-a may be coupled with the gateof transistor 505-c, and transistors 505-a and 505-c may be configuredto operate as a current mirror.

When amplifier component 410-a is configured to operate in the amplifiermode and has its inputs and outputs coupled as described above,amplifier component 410-a may operate as a voltage buffer that adjuststhe voltage of digit line 210-a V_(DL) 1105 from a first voltage (e.g.,the voltage at the end of the first portion, ˜V_(PRE)) to a secondvoltage (e.g., an offset-adjusted sense voltage, V_(SENSEOFF)). Theoffset-adjusted sense voltage may, in some cases, be the sense voltageV_(SENSE) adjusted by the voltage offset of amplifier component 410-a.

Similarly, the voltage at the first node 425 of amplifier capacitor 415(V_(AMPCAP) 1115), the voltage at the second input 440 of amplifiercomponent 410-a (V_(INPUT2) 1125), and/or the voltage at the secondoutput 460-a (V_(OUTPUT) 1130) of amplifier component 410-a may also beadjusted from a first voltage (e.g., the voltage to which they wereraised during a first portion of the read operation, such as a firstpre-charging portion) to a second voltage.

At time t3, a third portion (e.g., a signal development portion) of theread operation may begin, as described with respect to FIG. 8.

The third portion may include asserting a word line signal to couplememory cell 105-a with digit line 210-a. In some cases, the word linesignal may be asserted by raising the word line voltage V_(WL) 1110 toV_(HSA), as depicted in FIG. 11. Memory cell 105-a may then begin todischarge an amount of electric charge onto digit line 210-a.

The third portion may include deactivating switching component 260-f touncouple the second output 460-a of amplifier component 410-a from thesecond input 440-a of amplifier component, which may deactivate thefeedback line established during the second portion.

During the third portion, amplifier component 410-a may be configured inthe amplifier mode, with switching components 510-d and 510-c activatedand switching components 510-a, 510-b, 510-e, and 510-f deactivated,such that transistors 505-a and 505-c are configured to function as acurrent mirror. During the signal development portion, amplifiercomponent 410-a may amplify a difference between V_(INPUT1) 1120 (e.g.,V1, which may be a sense voltage V_(SENSE)) and the voltage ofV_(INPUT2) 1125 (e.g., the voltage of digit line 210-a, V_(DL)).

During the third portion, the second output 460-a of amplifier component410-a may be coupled with the first node 420 of amplifier capacitor 415by activating switching component 260-e, and the second node 425 ofamplifier capacitor 415 may be coupled with digit line 210-a. In thisconfiguration, amplifier component 410-a and amplifier capacitor 415 mayfunction as a current integrator. As a result, during the signaldevelopment portion, the amount of electric charge that is discharged bymemory cell 105-a onto digit line 210-a may be integrated by amplifiercomponent 410-a and amplifier capacitor 415, while the voltage V_(DL)1105 of digit line 210-a is set at or near (e.g., remains at or near)the second voltage (e.g., the offset-adjusted sense voltageV_(SENSEOFF)).

As depicted in FIG. 11, during the signal development portion of theread operation, the voltage V_(AMPCAP) 1115 at the first node 420 of theamplifier capacitor 415 changes as the electric charge is integrated.The amount of change in the voltage V_(AMPCAP) 1115 depends on whetherthe memory cell 105-a was storing a state of “0” or “1.”

At time t4, a fourth portion (e.g., a prepare to latch portion) of theread operation may begin, as described with respect to FIG. 9. Duringthe fourth portion, the amplifier component may be prepared for thelatch operation by activating switching components 510-e and 510-f toconfigure amplifier component 410-a to operate in the latch mode tocross-couple transistors 505-a and 505-c.

During the fourth portion, the digit line 210-a may be uncoupled fromthe second input 440-a of amplifier component 415 by deactivatingswitching component 260-d. The amplifier component 415 may be turned offor deactivated during the fourth portion by deactivating switchingcomponent 260-h to decouple the amplifier component 410-a from voltagesource 235-h (e.g., V_(SS)) and activating switching components 510-aand 510-b to couple amplifier component with voltage source V6 (e.g.,V_(HSA)). The first input 435-a of amplifier component 410-a may becoupled with voltage source 235-e, which may be associated with voltageV2 (e.g., a reference voltage V_(REF)); thus, at t4, the voltageV_(INPUT1) 1120 at the first input 435-b may rise towards V_(REF).

The second input 440-a may be coupled with the first node 420 ofamplifier capacitor 420 by activating switching component 260-f, andtherefore voltage V_(INPUT2) at second input 440-a may rise towardsV_(AMPCAP). As noted above, the voltage of V_(AMPCAP) may depend onwhether the memory cell 105-a was storing a state of “0” or “1,” thustwo states are represented.

At time t5, a fifth portion (e.g., a latch portion) of the readoperation may begin, when the amplifier component is activated (fired)while it is configured in the latch mode. The amplifier component 410-amay be activated by activating switching component 260-h to coupleamplifier component with voltage source 235-h and deactivating switchingcomponents 510-a and 510-b to decouple amplifier component from voltagesource 235-g.

When amplifier component 410-a is activated while configured in thelatch mode, amplifier component may determine the state of memory cell105-a by comparing the voltage of amplifier capacitor V_(AMPCAP) (asreceived at the second input 440-a, via V_(INPUT2) 1125) with areference voltage V_(REF) (as received at the first input 435-a, viaV_(INPUT1) 1120). For example, when the memory cell 105-b stores a logicstate 1, V_(AMPCAP) may be lower than V_(REF), while when the memorycell 105-b stores a logic state 0, V_(AMPCAP) may be higher thanV_(REF). Based on the comparison, the voltage at the second output 460-aof amplifier component 415 (V_(OUTPUT) 1130) may reflect a voltageassociated with a logic state of 1 or 0.

Amplifier component may, in some examples, store the state internally(e.g., using transistors 505-a and 505-c) and output the stored state toan external component, or amplifier component may, in some examples,output the state (e.g., to a separate latch circuit) without storing thestate internally.

Although illustrated in FIG. 11 as separate operations occurring atdifferent times, certain operations may occur simultaneously,concurrently, or in a different order. In some examples, variousoperations may be advantageously initiated simultaneously orconcurrently to reduce the amount of time for sensing a logic state ofthe memory cell 105-b.

The order of operations shown in timing diagram 1100 is for illustrationonly, and various other orders and combinations of steps may beperformed to support sense amplifiers with lower offset and higher speedfor sensing memory cells in accordance with the present disclosure.Further, the timing of the operations of the timing diagram 1100 is alsofor illustration purposes only, and is not meant to indicate aparticular relative duration between one operation and another. Variousoperations may occur over a duration that is relatively shorter orrelatively longer than illustrated in various examples of senseamplifiers with lower offset and higher speed for sensing memory cellsin accordance with the present disclosure.

The transitions of the logical signals of the timing diagram 1100 areillustrative of transitions from one state to another, and generallyreflect transitions between a disabled or deactivated state (e.g., state“0”) and an enabled or activated state (e.g., state “1”) as associatedwith a particular operation. In various examples the states may beassociated with a particular voltage of the logical signal (e.g., alogical input voltage applied to a gate of a transistor operating as aswitch), and the change in voltage from one state to another may not beinstantaneous. Rather, in some examples, a voltage associated with alogical signal may follow a ramping behavior, or time-constant (e.g.,logarithmic or exponential) behavior over time from one logical state toanother.

In some examples, the transition of a component from one state toanother may be based at least in part on characteristics of theassociated logical signal, including the voltage level of the logicalsignal or the transition characteristics of the logical signal itself.Thus, the transitions shown in timing diagram 1100 are not necessarilyindicative of an instantaneous transition. Further, the initial state ofa logical signal associated with a transition at a numbered operationmay have been arrived during various times preceding the numberedoperation while still supporting the described transitions andassociated operations. Although logical signals are shown as atransition between logical states, the voltage of a logical signal maybe selected to operate a component at a particular working point (e.g.,in an active region or in a saturation region), and may be the same as,or different from a voltage of other logical signals.

Although FIGS. 5-11 have been discussed with respect to an amplifiercomponent that may be configurable to operate, while in a latch mode, asa half latch, alternative examples of amplifier component 410 may beconfigurable to operate as a full latch, as discussed with respect toFIGS. 12-14.

FIG. 12 illustrates an example of a circuit 1200 that supports senseamplifiers with lower offsets and higher speeds for sensing memory cellsin accordance with various examples of the present disclosure. Circuit1200 provides additional detail with respect to the circuitry of anamplifier component 410-b, which may be an example of amplifiercomponent 410 described with respect to FIG. 4 and which may besubstituted for amplifier component 410-a as described with respect toFIGS. 5-11.

Circuit 1200 may depict an example of an amplifier component that may beconfigurable to operate, in a latch mode, as a full latch. Amplifiercomponent 410-b may, in some cases, operate in a manner similar to thatdescribed with respect to amplifier 410-a in FIGS. 5-11 during a readoperation of a memory cell. However, amplifier component 410-b includesadditional circuitry with respect to amplifier component 410-a to enableamplifier component 410-b to be configurable to operate as a full latch.Accordingly, a separate latch circuit (e.g., latch circuit 430) may notbe used in memory devices that include amplifier component 410-b.

Relative to amplifier component 410-a, amplifier component 410-bincludes additional switching components 510-k and 510-l and associatedadditional conductive lines to enable cross-coupling of transistors505-b, 505-d. Amplifier component 410-b may be coupled with voltagesources 235-h, 235-g, and 235-j via switching component 260-h andvoltage supply selection component 245-c, switching component 260-i, andswitching component 260-j, respectively. In some examples, voltagesource 235-j is associated with voltage V8, which may be a supplyvoltage. In some examples, voltage sources 235-h and voltage source235-j are each associated with the same supply voltage (e.g., V_(SS)).Amplifier component 410-b may be activated by activating switchingcomponent 260-h and voltage supply selection component 245-c, or byactivating switching component 260-j.

In some examples, voltage supply 235-j and switching component 260-j maybe optional. In some examples, the addition of voltage source 235-j mayprovide additional flexibility with respect to using the same controlsignal to couple a voltage supply (e.g., V_(SS)) with the amplifiercomponent 410-b and to configure the amplifier component 410-b in theamplifier mode or the latch mode. For example, a memory device may usethe same control signal to activate switching components 260-j andswitching components 510 i, 510-j, 510-k, and 510-l to configure andfire amplifier component 410-b in a latch mode.

Amplifier component 410-b includes a first input 435-b, a second input440-b, a first output 455-b, and a second output 460-b. In someexamples, first input 435-b may be referred to as a positive input, andsecond input 440-b may be referred to as a negative input or feedbackinput. In some examples, first output 455-b and second output 460-b maybe inverses of each other; that is, a voltage or current at first output455-b may be the opposite of a voltage or current at second output460-b.

Amplifier component 410-b includes various internal transistors 505 andswitching components 510. In some examples, transistors 505 may be MOStransistors. In some cases, transistors 505-e and 505-g may be PMOStransistors. In some cases, transistors 505-f and 505-h may be eitherPMOS transistors or NMOS transistors. Other examples of an amplifiercomponent 410-b may use other types of transistors.

In some cases, switching components 510-i, 510-j, 510-k, and 510-l maybe CMOS switching components (e.g., including both PMOS and NMOStransistors) to enable these switching components to pass 0 and V_(HSA)voltages. In some cases, switching components 510-d and 510-d can bePMOS, NMOS, or CMOS switching components.

As discussed with respect to amplifier component 410-a, switchingcomponents 510 in amplifier component 410-b may be used to couple oruncouple various nodes of transistors 505 with each other and/or withinputs or outputs of amplifier component 410-b and thereby configureamplifier component 410-b to operate in an amplifier mode or a latchmode, as discussed with respect to FIGS. 13-14.

FIG. 13 illustrates an example of a circuit 1300 that supports senseamplifiers with lower offsets and higher speeds for sensing memory cellsin accordance with various examples of the present disclosure. Circuit1300 depicts amplifier component 410-b as configured to operate in anamplifier mode, such as during a second pre-charging portion of a readoperation or during a signal development portion of a read operation asdiscussed with respect to FIGS. 5 and 8.

In the example depicted in FIG. 13, amplifier component 410-b may beconfigured to operate in an amplifier mode by activating switchingcomponent 510-h and 510-g deactivating switching components 510-i,510-j, 510-k, and 510-l. In this configuration, transistors 505-e and505-g are configured to operate as a current mirror. Amplifier component410-b may be turned on or activated by activating switching components260-h and 260-i and voltage supply selection component 245-c to coupleamplifier component 410-b with voltage sources 235-h and 235-g.

FIG. 14 illustrates an example of a circuit 1400 that supports senseamplifiers with lower offsets and higher speeds for sensing memory cellsin accordance with various examples of the present disclosure. Circuit1400 depicts amplifier component 410-b as configured to operate in alatch mode, such during a latch portion of a read operation as discussedwith respect to FIG. 10.

In the example depicted in FIG. 14, amplifier component 410-b may beconfigured to operate in the latch mode by activating switchingcomponents 510-i, 510-j, 510-k, and 510-l and deactivating switchingcomponents 510-g and 510-h. In this configuration, transistors 505-a,505-b, 505-c, and 505-c are cross-coupled and configured to operate as afull latch. Amplifier component 410-b may be activated by activatingswitching component 260-j to couple amplifier component with voltagesource 235-j (e.g., V_(SS)). In some examples, the same control signalmay be used to activate switching components 260-j, 510-i, 510-j, 510-k,and 510-l.

FIG. 15 shows a block diagram 1500 of a memory device 1505 that maysupport sense amplifiers with lower offset and higher speed for sensingmemory cells in accordance with various examples of the presentdisclosure. The memory device 1505 may be referred to as an electronicmemory apparatus, and may be an example of a component of a memorydevice 100 as described with reference to FIG. 1.

The memory device 1505 may include one or more memory cells 1510, whichmay be an example of memory cells 105 described with reference to FIGS.1 through 14. The memory device 1505 may also include a memorycontroller 1515, a word line 1520, a plate line 1525, a sense component1535, and a digit line 1540. These components may be in electroniccommunication with each other and may perform one or more of thefunctions described herein in accordance with aspects of the disclosure.In some cases, the memory controller 1515 may include a biasingcomponent 1550 and a timing component 1455.

The memory controller 1515 may be in electronic communication with theword line 1520, the plate line 1525, the digit line 1540, and the sensecomponent 1535, which may be examples of a word line 205, a plate line215, a digit line 210, a reference line 255, and a sense component 130described with reference to FIGS. 1 through 14. In some examples, thememory device 1505 may also include a latch 1545, which may be anexample of a latch circuit 430 or an I/O component 150 as describedherein. The components of the memory device 1505 may be in electroniccommunication with each other and may perform examples of the functionsdescribed with reference to FIGS. 1 through 14. In some cases, the sensecomponent 1535 or latch 1545 may be components of memory controller1515.

In some examples, the digit line 1540 may be in electronic communicationwith the sense component 1535 and a ferroelectric capacitor of a memorycell 1510. A memory cell 1510 may be writable with a logic state (e.g.,a first or second logic state). The word line 1520 may be in electroniccommunication with the memory controller 1515 and a cell selector of amemory cell 1510. The plate line 1525 may be in electronic communicationwith the memory controller 1515 and a plate of the ferroelectriccapacitor of a memory cell 1510. The sense component 1535 may be inelectronic communication with the memory controller 1515, the digit line1540, and the latch 1545. In some examples, a common access line mayprovide the functions of a signal line and a reference line. The sensecontrol line 1530 may be in electronic communication with the sensecomponent 1535 and the memory controller 1515. These components may alsobe in electronic communication with other components, inside, oroutside, or both of the memory device 1505, in addition to componentsnot listed above, via other components, connections, or busses.

The memory controller 1515 may be an example of a memory controller 150as described herein, and may be configured to activate the word line1520, the plate line 1525, and/or the digit line 1540 by applyingvoltages to various nodes. For example, the biasing component 1550 maybe configured to apply a voltage to operate the memory cell 1510 to reador write the memory cell 1510 as described above. In some cases, thememory controller 1515 may include a row decoder, column decoder, orboth, as described with reference to FIG. 1, which may enable the memorycontroller 1515 to access one or more memory cells 105. The biasingcomponent 1550 may also provide voltage potentials to the memory cell1510 to generate a reference signal for the sense component 1535.Additionally or alternatively, the biasing component 1550 may providevoltage potentials for the operation of the sense component 1535.

In some cases, the memory controller 1515 may perform one or more of itsoperations using the timing component 1555. For example, the timingcomponent 1555 may control the timing of the various word lineselections or plate biasing, including timing for switching and voltageapplication to perform the memory functions, such as reading andwriting, discussed herein (e.g., in accordance with operations describedwith reference to timing diagram 1100 of FIG. 11). In some cases, thetiming component 1555 may control the operations of the biasingcomponent 1550.

The sense component 1535 may compare a sense signal from the memory cell1510 (e.g., via digit line 1540) with a reference signal (e.g., viareference line 1560). The reference signal may be received from avoltage source, for example, or from memory cell 1510. The sensecomponent 1535 may include one or more amplifier components inelectronic communication with the latch and the ferroelectric memorycell. Upon determining the logic state, the sense component 1535 maythen store the state in an amplifier component in the sense component(e.g., amplifier component 410 as described with respect to FIGS. 4-14)or may store the state in the latch 1545, where it may be used inaccordance with the operations of an electronic device that may includethe memory device 1505.

The memory controller 1515, or its sub-components, may be implemented inhardware, code (e.g., software, firmware) executed by a processor, orany combination thereof. If implemented in code executed by a processor,the functions of the memory controller 1515, or its sub-components, maybe executed by a general-purpose processor, a digital signal processor(DSP), an application-specific integrated circuit (ASIC), anfield-programmable gate array (FPGA) or other programmable logic device,discrete gate or transistor logic, discrete hardware components, or anycombination thereof designed to perform the functions described in thepresent disclosure.

The memory controller 1515, or its sub-components, may be physicallylocated at various positions, including being distributed such thatportions of functions are implemented at different physical locations byone or more physical devices. In some examples, the memory controller1515, or its sub-components, may be a separate and distinct component inaccordance with various examples of the present disclosure. In otherexamples, the memory controller 1515, or its sub-components, may becombined with one or more other hardware components, including but notlimited to an I/O component, a transceiver, a network server, anothercomputing device, one or more other components described in the presentdisclosure, or a combination thereof in accordance with various examplesof the present disclosure. The memory controller 1515 may be an exampleof the memory controller 1715 described with reference to FIG. 17.

In some examples, the memory controller 1515, including anysubcomponents thereof, may support coupling, during a signal developmentportion of a read operation of a memory cell, a ferroelectric capacitorof the memory cell with a digit line associated with the memory cell toadjust an amount of electric charge on the digit line; coupling, duringthe signal development portion, a first input of an amplifier componentwith the digit line to amplify a voltage of the digit line; decoupling,after the signal development portion of the read operation, the firstinput of the amplifier component from the digit line; configuring theamplifier component to operate in a latch mode based at least in part onactivating or deactivating a first switching component in the amplifier;and outputting, on a first output of the amplifier, a state of thememory cell while the amplifier component operates in the latch mode.

In some examples, the memory controller 1515, including anysubcomponents thereof, may support activating or deactivating switchingcomponents in memory device 1505 (e.g., in sense component, senseamplifier, and/or amplifier component) by providing control signals tosuch switching components. In this manner, memory controller 1515 maysupport configuring an amplifier component in an amplifier mode or alatch mode by providing control signals to switching components withinamplifier component to activate or deactivate the switching components.

FIG. 16 shows a block diagram 1600 of a memory controller 1615 that maysupport sense amplifiers with lower offset and higher speed for sensingmemory cells in accordance with various examples of the presentdisclosure. The memory controller 1615 may be an example of a memorycontroller 150 described with reference to FIG. 1 or a memory controller1515 described with reference to FIG. 15. The memory controller 1615 mayinclude a biasing component 1620 and a timing component 1625, which maybe examples of biasing component 1550 and timing component 1555described with reference to FIG. 15. The memory controller 1615 may alsoinclude a voltage selector 1630, a memory cell selector 1635, and asense controller 1640. Each of these modules may communicate, directlyor indirectly, with one another (e.g., via one or more buses).

The voltage selector 1630 may initiate the selection of voltage sourcesto support various access operations of a memory device. For example,the voltage selector 1630 may generate logical signals used to activateor deactivate various switching components, such as the switchingcomponents 260 or the selection components 245 described with referenceto FIGS. 4-13. For example, the voltage selector 1630 may generate oneor more of the logical signals for selecting (e.g., enabling, disabling)the voltage sources 235 of the timing diagram 1100 described withreference to FIG. 11.

The memory cell selector 1635 may select a memory cell for sensingoperations. For example, the memory cell selector 1635 may generatelogical signals used to activate or deactivate a cell selector, such asselection component 245 described with reference to FIG. 2. For example,the memory cell selector 1635 may generate the word line signal oftiming diagram 1100 described with reference to FIG. 11.

The sense controller 1640 may control various operations of a sensecomponent, such as the sense components 130 described with reference toFIGS. 1 through 14. For example, the sense controller 1640 may generatelogical signals used to activate or deactivate a switching component,such as the switching components 260 described with reference to FIGS.4-14. In some examples, the sense controller 1640 may generate logicalsignals used to couple or decouple a sense component with a sensingvoltage source, which may include activating or deactivating switchingcomponents such as switching components 260-h, 260-i, 260-j, orselection components 245 as described with reference to FIGS. 4-14.

In some examples, the sense controller 1640 may compare a voltage of afirst input of an amplifier component with a voltage of a second inputof the amplifier component, where the voltages are based on (e.g.,result from) accessing the memory cell with one or more accessoperations of a read operation. The sense controller 1640 may determinea logic value associated with the memory cell based on comparing theresultant voltages. In some examples, the sense controller 1640 mayprovide signals to another component to determine the logic valueassociated with the memory cell.

FIG. 17 shows a diagram of a system 1700 including a device 1705 thatmay support sense amplifiers with lower offset and higher speed forsensing memory cells in accordance with various examples of the presentdisclosure. The device 1705 may be an example of or include thecomponents of memory device 100 as described above, for example, withreference to FIG. 1. The device 1705 may include components forbi-directional communications including components for transmitting andreceiving communications, including a memory controller 1715, memorycells 1720, a basic input/output system (BIOS) component 1725, aprocessor 1730, an I/O component 1735, and peripheral components 1740.These components may be in electronic communication via one or morebusses (e.g., bus 1710).

The memory controller 1715 may operate one or more memory cells asdescribed herein. Specifically, the memory controller 1715 may beconfigured to support the described sense amplifiers for sensing a logicstate of a memory cell. In some cases, the memory controller 1715 mayinclude a row decoder, column decoder, or both, as described withreference to FIG. 1 (not shown).

The memory cells 1720 may be an example of memory cells 105 or 1410described with reference to FIGS. 1 through 14, and may storeinformation (e.g., in the form of a logic state) as described herein.

The BIOS component 1725 be a software component that includes BIOSoperated as firmware, which may initialize and run various hardwarecomponents. The BIOS component 1725 may also manage data flow between aprocessor and various other components, such as peripheral components,I/O control components, and others. The BIOS component 1725 may includea program or software stored in read only memory (ROM), flash memory, orany other non-volatile memory.

The processor 1730 may include an intelligent hardware device, (e.g., ageneral-purpose processor, a DSP, a central processing unit (CPU), amicrocontroller, an ASIC, an FPGA, a programmable logic device, adiscrete gate or transistor logic component, a discrete hardwarecomponent). In some cases, the processor 1730 may be configured tooperate a memory array using a memory controller. In other cases, amemory controller may be integrated into the processor 1730. Theprocessor 1730 may be configured to execute computer-readableinstructions stored in a memory to perform various functions (e.g.,functions or tasks supporting self-referencing sensing schemes foraccessing memory cells).

The I/O component 1735 may manage input and output signals for thedevice 1705. The I/O component 1735 may also manage peripherals notintegrated into the device 1705. In some cases, the I/O component 1735may represent a physical connection or port to an external peripheral.In some cases, the I/O component 1735 may utilize an operating systemsuch as iOS®, ANDROID®, MS-DOS®, MS-WINDOWS®, OS/2®, UNIX®, LINUX®, oranother known operating system. In other cases, the I/O component 1735may represent or interact with a modem, a keyboard, a mouse, atouchscreen, or a similar device. In some cases, the I/O component 1735may be implemented as part of a processor. In some cases, a user mayinteract with the device 1705 via the I/O component 1735 or via hardwarecomponents controlled by the I/O component 1735. The I/O component 1735may support accessing the memory cells 1720, including receivinginformation associated with the sensed logic state of one or more of thememory cells 1720, or providing information associated with writing alogic state of one or more of the memory cells 1720.

The peripheral components 1740 may include any input or output device,or an interface for such devices. Examples may include disk controllers,sound controller, graphics controller, Ethernet controller, modem,universal serial bus (USB) controller, a serial or parallel port, orperipheral card slots, such as peripheral component interconnect (PCI)or accelerated graphics port (AGP) slots.

The input 1745 may represent a device or signal external to the device1705 that provides input to the device 1705 or its components. This mayinclude a user interface or an interface with or between other devices.In some cases, the input 1745 may be managed by the I/O component 1735,and may interact with the device 1705 via a peripheral component 1740.

The output 1750 may represent a device or signal external to the device1705 configured to receive output from the device 1705 or any of itscomponents. Examples of the output 1750 may include a display, audiospeakers, a printing device, another processor or printed circuit board,or other devices. In some cases, the output 1750 may be a peripheralelement that interfaces with the device 1705 via the peripheralcomponent(s) 1740. In some cases, the output 1750 may be managed by theI/O component 1735.

The components of the device 1705 may include circuitry designed tocarry out their functions. This may include various circuit elements,for example, conductive lines, transistors, capacitors, inductors,resistors, amplifiers, or other active or inactive elements, configuredto carry out the functions described herein. The device 1705 may be acomputer, a server, a laptop computer, a notebook computer, a tabletcomputer, a mobile phone, a wearable electronic device, a personalelectronic device, or the like. Or the device 1705 may be a portion orelement of such a device.

FIG. 18 shows a flowchart illustrating a method 1800 that may supportsense amplifiers with lower offset and higher speed for sensing memorycells in accordance with various examples of the present disclosure. Theoperations of method 1800 may be implemented by memory device 100,circuit 200, circuits 400-1000 and 1200-1400, memory device 1405, system800, or their components as described herein. For example, operations ofmethod 1800 may be performed at least in part by a memory controller asdescribed with reference to FIGS. 1 through 17. In some examples, amemory device may execute a set of instructions to control thefunctional elements of the device (e.g., voltage supplies, logicalsignals, transistors, amplifier components, sense amplifiers, switchingcomponents, selection components) to perform the functions describedbelow. Additionally or alternatively, the memory device may perform someor all of the functions described below using special-purpose hardware.

At 1805 the memory device may couple, during a signal developmentportion of a read operation of a memory cell (e.g., memory cell 105), aferroelectric capacitor (e.g., capacitor 220) of the memory cell with adigit line (e.g., digit line 210) associated with the memory cell toadjust an amount of electric charge on the digit line. In some cases,the memory device may couple the ferroelectric capacitor with the digitline by activating one or more switching components (e.g., switchingcomponent 260-d), such as described with respect to FIGS. 4-14.

At 1810, the memory device may couple, during the signal developmentportion, a first input of an amplifier component (e.g., input 440 ofamplifier component 410) with the digit line to amplify a voltage of thedigit line. In some cases, the memory device may couple the first inputof the amplifier component with the digit line by activating one or moreswitching components (e.g., switching component 260-d). In some cases,the amplifier component may amplify the voltage of the digit line byamplifying a difference between the voltage of the digit line and asense voltage (e.g., from voltage source 235-d), such as described withrespect to FIG. 8.

At 1815, the memory device may uncouple, after the signal developmentportion of the read operation, the first input of the amplifiercomponent from the digit line. In some cases, the memory device mayuncouple the first input of the amplifier component from the digit lineby deactivating one or more switching components (e.g., switchingcomponent 260-d), such as described with respect to FIG. 9.

At 1820, the memory device may configure the amplifier component tooperate in a latch mode based at least in part on activating ordeactivating a first switching component (e.g., by activating switchingcomponent 510-e, 510-f and/or deactivating switching component 510-d,510-c) in the amplifier component.

At 1825, the memory device may output, on a first output (e.g., onoutput 460) of the amplifier component, a state of the memory cell whilethe amplifier operates in the latch mode. In some cases, the memorydevice may output the state to a separate latch circuit (e.g., latchcircuit 430), which stores the state. In some cases, the memory devicemay store the state using transistors within amplifier component (e.g.,transistors 505-a, 505-b), and may output the state to other componentsof memory device.

Memory device 100 may perform some or all of the processes describedabove with respect to method 1800 using the circuitry and signalsdescribed with respect to FIGS. 1-17, for example.

It should be noted that the methods described above describe possibleimplementations, and that the operations and the steps may be rearrangedor otherwise modified and that other implementations are possible.Further, examples from two or more of the methods may be combined.

An apparatus for performing the method 1800 is described. The apparatusmay include means for coupling, during a signal development portion of aread operation of a memory cell, a ferroelectric capacitor of the memorycell with a digit line associated with the memory cell to adjust anamount of electric charge on the digit line; means for coupling, duringthe signal development portion, a first input of an amplifier componentwith the digit line to amplify a voltage of the digit line; means fordecoupling, after the signal development portion of the read operation,the first input of the amplifier component from the digit line; meansfor configuring the amplifier component to operate in a latch mode basedat least in part on activating or deactivating a first switchingcomponent in the amplifier component; and means for outputting, on afirst output of the amplifier component, a state of the memory cellwhile the amplifier component operates in the latch mode.

The description herein provides examples, and is not limiting of thescope, applicability, or examples set forth in the claims. Changes maybe made in the function and arrangement of elements discussed withoutdeparting from the scope of the disclosure. Various examples may omit,substitute, or add various procedures or components as appropriate.Also, features described with respect to some examples may be combinedin other examples.

Information and signals described herein may be represented using any ofa variety of different technologies and techniques. For example, data,instructions, commands, information, signals, bits, symbols, and chipsthat may be referenced throughout the above description may berepresented by voltages, currents, electromagnetic waves, magneticfields or particles, optical fields or particles, or any combinationthereof. Some drawings may illustrate signals as a single signal;however, it will be understood by a person of ordinary skill in the artthat the signal may represent a bus of signals, where the bus may have avariety of bit widths.

As used herein, the term “virtual ground” refers to a node of anelectrical circuit that is held at a voltage of approximately zero volts(0V), or more generally represents a reference voltage of the electricalcircuit or device including the electrical circuit, which may or may notbe directly coupled with ground. Accordingly, the voltage of a virtualground may temporarily fluctuate and return to approximately 0V, orvirtual 0V, at steady state. A virtual ground may be implemented usingvarious electronic circuit elements, such as a voltage dividerconsisting of operational amplifiers and resistors. Otherimplementations are also possible. “Virtual grounding” or “virtuallygrounded” means connected to approximately 0V, or some other referencevoltage of a device.

The term “electronic communication” and “coupled” refers to arelationship between components that supports electron flow between thecomponents. This may include a direct connection or coupling betweencomponents or may include intermediate components. In other words,components that are “connected with” or “coupled with” are in electroniccommunication with each other. By way of example, two components may becoupled by activating or deactivating a switching component (e.g., atransistor) to enable electronic communication between the twocomponents.

The phrase “coupled between” may refer to an order of components inrelation to each other, and may refer to an electrical coupling. In oneexample, a component “B” that is electrically coupled between acomponent “A” and a component “C” may refer to an order of components of“A-B-C” or “C-B-A” in an electrical sense. In other words, electricalsignals (e.g., voltage, charge, current) may be passed from component Ato component C by way of component B.

A description of a component B being “coupled between” component A andcomponent C should not necessarily be interpreted as precluding otherintervening components in the described order. For example, a component“D” may be coupled between the described component A and component B(e.g., referring to an order of components of “A-D-B-C” or “C-B-D-A” asexamples), while still supporting component B being electrically coupledbetween component A and component C. In other words, the use of thephrase “coupled between” should not be construed as necessarilyreferencing an exclusive sequential order.

Further, a description of component B being “coupled between” componentA and component C does not preclude a second, different coupling betweencomponent A and component C. For example, component A and component Cmay be coupled with each other in a separate coupling that iselectrically parallel with a coupling via component B. In anotherexample, component A and component C may be coupled via anothercomponent “E” (e.g., component B being coupled between component A andcomponent C and component E being coupled between component A andcomponent C). In other words, the use of the phrase “coupled between”should not be construed as an exclusive coupling between components.

The term “isolated” refers to a relationship between components in whichelectrons are not presently capable of flowing between them; componentsare isolated from each other if there is an open circuit between them.For example, two components physically coupled by a switching componentmay be isolated from each other when the switching component is open ordeactivated.

As used herein, the term “shorting” refers to a relationship betweencomponents in which a conductive path is established between thecomponents via the activation of a single intermediary component betweenthe two components in question. For example, a first component shortedto a second component may exchange electrons with the second componentwhen a switching component between the two components is closed. Thus,shorting may be a dynamic operation that enables the application ofvoltage and/or flow of charge between components (or lines) that are inelectronic communication.

As used herein, the term “electrode” may refer to an electricalconductor, and in some cases, may be employed as an electrical contactto a memory cell or other component of a memory array. An electrode mayinclude a trace, wire, conductive line, conductive layer, or the likethat provides a conductive path between elements or components of memorydevice 100.

As used herein, the term “terminal” need not suggest a physical boundaryor connection point of a circuit element. Rather, “terminal” may referto a reference point of a circuit relevant to the circuit element, whichmay also be referred to as a “node” or “reference point.”

The term “layer” used herein refers to a stratum or sheet of ageometrical structure. each layer may have three dimensions (e.g.,height, width, and depth) and may cover some or all of a surface. Forexample, a layer may be a three-dimensional structure where twodimensions are greater than a third, such as a thin-film. Layers mayinclude different elements, components, and/or materials. In some cases,one layer may be composed of two or more sublayers. In some of theappended figures, two dimensions of a three-dimensional layer aredepicted for purposes of illustration. Those skilled in the art will,however, recognize that the layers are three-dimensional in nature

A transistor or transistors discussed herein may represent afield-effect transistor (FET) and comprise a three terminal deviceincluding a source, drain, and gate. The terminals may be connected toother electronic elements through conductive materials, such as metals.The source and drain may be conductive and may comprise a heavily-doped,or degenerate semiconductor region. The source and drain may beseparated by a lightly-doped semiconductor region or channel. If thechannel is n-type (e.g., majority carriers are electrons), then the FETmay be referred to as a n-type FET. If the channel is p-type (e.g.,majority carriers are holes), then the FET may be referred to as ap-type FET. The channel may be capped by an insulating gate oxide. Thechannel conductivity may be controlled by applying a voltage to thegate. For example, applying a positive voltage or negative voltage to ann-type FET or a p-type FET, respectively, may result in the channelbecoming conductive. A transistor may be “on” or “activated” when avoltage greater than or equal to the transistor's threshold voltage isapplied to the transistor gate. The transistor may be “off” or“deactivated” when a voltage less than the transistor's thresholdvoltage is applied to the transistor gate.

The description set forth herein, in connection with the appendeddrawings, describes example configurations and does not represent allthe examples that may be implemented or that are within the scope of theclaims. The term “exemplary” used herein means “serving as an example,instance, or illustration,” and not “preferred” or “advantageous overother examples.” The detailed description includes specific details forthe purpose of providing an understanding of the described techniques.These techniques, however, may be practiced without these specificdetails. In some instances, well-known structures and devices are shownin block diagram form to avoid obscuring the concepts of the describedexamples.

In the appended figures, similar components or features may have thesame reference label. Further, various components of the same type maybe distinguished by following the reference label by a dash and a secondlabel that distinguishes among the similar components. If just the firstreference label is used in the specification, the description isapplicable to any one of the similar components having the same firstreference label irrespective of the second reference label.

The various illustrative blocks and modules described in connection withthe disclosure herein may be implemented or performed with ageneral-purpose processor, a DSP, an ASIC, an FPGA or other programmablelogic device, discrete gate or transistor logic, discrete hardwarecomponents, or any combination thereof designed to perform the functionsdescribed herein. A general-purpose processor may be a microprocessor,but in the alternative, the processor may be any conventional processor,controller, microcontroller, or state machine. A processor may also beimplemented as a combination of computing devices (e.g., a combinationof a digital signal processor (DSP) and a microprocessor, multiplemicroprocessors, one or more microprocessors in conjunction with a DSPcore, or any other such configuration).

The functions described herein may be implemented in hardware, softwareexecuted by a processor, firmware, or any combination thereof. Ifimplemented in software executed by a processor, the functions may bestored on or transmitted over as one or more instructions or code on acomputer-readable medium. Other examples and implementations are withinthe scope of the disclosure and appended claims. For example, due to thenature of software, functions described above can be implemented usingsoftware executed by a processor, hardware, firmware, hardwiring, orcombinations of any of these. Features implementing functions may alsobe physically located at various positions, including being distributedsuch that portions of functions are implemented at different physicallocations. Also, as used herein, including in the claims, “or” as usedin a list of items (for example, a list of items prefaced by a phrasesuch as “at least one of” or “one or more of”) indicates an inclusivelist such that, for example, a list of at least one of A, B, or C meansA or B or C or AB or AC or BC or ABC (e.g., A and B and C).

As used herein, the term “substantially” means that the modifiedcharacteristic (e.g., a verb or adjective modified by the term“substantially”) need not be absolute but is close enough so as toachieve the advantages of the characteristic, or close enough that thecharacteristic referred to is true in the context of the relevantaspects of the disclosure.

As used herein, the phrase “based on” shall not be construed as areference to a closed set of conditions. For example, an exemplary stepthat is described as “based on condition A” may be based on both acondition A and a condition B without departing from the scope of thepresent disclosure. In other words, as used herein, the phrase “basedon” shall be construed in the same manner as the phrase “based at leastin part on.”

The description herein is provided to enable a person skilled in the artto make or use the disclosure. Various modifications to the disclosurewill be readily apparent to those skilled in the art, and the genericprinciples defined herein may be applied to other variations withoutdeparting from the scope of the disclosure. Thus, the disclosure is notlimited to the examples and designs described herein, but is to beaccorded the broadest scope consistent with

What is claimed is:
 1. A method, comprising: applying, by a componentwhile configured in an amplifier mode, a first voltage to a digit linethat is coupled with a memory cell based at least in part on a firstsignal having the first voltage being applied at a first input of thecomponent, wherein a logic state is stored at the memory cell;outputting, by the component while configured in a latch mode, a secondvoltage to another component based at least in part on comparing asecond signal applied at the first input of the component and a thirdsignal received at a second input of the component, wherein the thirdsignal is based at least in part on the logic state of the memory cell;and storing, by the component while configured in the latch mode, thesecond voltage, wherein the second voltage is based at least in part onthe logic state of the memory cell.
 2. The method of claim 1, whereinthe second voltage corresponds to a first logic state, and wherein thestoring comprises: storing the second voltage within the component basedat least in part on the second voltage corresponding to the first logicstate.
 3. The method of claim 1, wherein the second voltage correspondsto a second logic state, and wherein the storing comprises: outputtingthe second voltage to an external latch based at least in part on thesecond voltage corresponding to the second logic state.
 4. The method ofclaim 1, further comprising: configuring, by the component, a firstconfiguration associated with the latch mode based at least in part onapplying the first voltage to the digit line, wherein configuring thefirst configuration comprises: activating a first switching componentthat is coupled with a gate of a first transistor and a node of a secondtransistor; and activating a second switching component that is coupledwith a gate of the second transistor and a node of the first transistor.5. The method of claim 4, wherein configuring the first configurationfurther comprises: deactivating a third switching component that iscoupled with the gate of the first transistor and a voltage source;deactivating a fourth switching component that is coupled with the gateof the second transistor and the voltage source; deactivating a fifthswitching component that is coupled with the gate of the firsttransistor and the gate of the second transistor; and deactivating asixth switching component that is coupled with the gate of the firsttransistor and the node of the first transistor.
 6. The method of claim5, further comprising: configuring, at the component, a secondconfiguration associated with the amplifier mode, wherein configuringthe second configuration comprises: activating the fifth switchingcomponent and the sixth switching component; deactivating the firstswitching component, the second switching component, the third switchingcomponent, and the fourth switching component.
 7. The method of claim 1,further comprising: receiving, at the first input of the component whileconfigured in the amplifier mode, the first signal, wherein a magnitudeof the first voltage is associated with sensing the logic state of thememory cell, and wherein an output of the component is coupled with thesecond input of the component and the digit line.
 8. The method of claim1, further comprising: receiving, at the first input of the componentwhile configured in the latch mode and after applying the first voltageto the digit line, the second signal having a third voltage; andcomparing, by the component while configured in the latch mode, thesecond signal with the third signal, wherein the second signal comprisesa reference voltage and the third signal is based at least in part onthe logic state of the memory cell.
 9. A method, comprising:maintaining, by a component while configured in an amplifier mode, adigit line at a first voltage during a sensing operation based at leastin part on a signal having the first voltage being applied at a firstinput of the component, wherein the digit line is coupled with a memorycell storing a logic state; sensing, by the component while configuredin a latch mode, the logic state of the memory cell; and storing, by thecomponent while configured in the latch mode, a second voltagecorresponding to the logic state of the memory cell.
 10. The method ofclaim 9, wherein the storing comprises: storing the second voltagewithin the component when the second voltage corresponds to a firstlogic state; and outputting the second voltage to an external latch whenthe second voltage corresponds to a second logic state.
 11. The methodof claim 9, further comprising: receiving one or more signals associatedwith configuring the latch mode at the component; and configuring afirst transistor and a second transistor in a cross-coupledconfiguration based at least in part on receiving the one or moresignals.
 12. The method of claim 11, further comprising: receiving oneor more signals associated with configuring the amplifier mode at thecomponent; and configuring the first transistor and the secondtransistor in a current mirror configuration based at least in part onreceiving the one or more signals.
 13. The method of claim 9, whereincharge transferred between the memory cell and the digit line during themaintaining generates a third voltage across a capacitor positionedbetween an output of the component and the digit line, and wherein thesensing is based at least in part on the third voltage.
 14. Anapparatus, comprising: a plurality of transistors, wherein an output ofthe plurality of transistors is coupled with a digit line that iscoupled with a memory cell; and a plurality of switching componentsconfigurable in a first configuration for configuring the plurality oftransistors in a cross-coupled configuration and configurable in asecond configuration for configuring the plurality of transistors in acurrent mirror configuration.
 15. The apparatus of claim 14, furthercomprising: a first voltage pin configured to couple the apparatus to afirst voltage source; and a first transistor of the plurality oftransistors comprising a first node coupled with the first voltage pinand comprising a second node; and a second transistor of the pluralityof transistors comprising a first node coupled with the first voltagepin and comprising a second node.
 16. The apparatus of claim 15, whereinthe first configuration comprises: a first switching component of theplurality of switching components configured to couple a gate of thefirst transistor to the second node of the second transistor; and asecond switching component of the plurality of switching componentsconfigured to couple the gate of the second transistor to the secondnode of the first transistor.
 17. The apparatus of claim 16, wherein thefirst configuration comprises: a third switching component of theplurality of switching components configured to isolate the gate of thefirst transistor from the first voltage pin; a fourth switchingcomponent of the plurality of switching components configured to isolatethe gate of the second transistor from the first voltage pin; a fifthswitching component of the plurality of switching components configuredto isolate the gate of the first transistor from the gate of the secondtransistor; and a sixth switching component of the plurality ofswitching components configured to isolate the gate of the firsttransistor from the second node of the first transistor.
 18. Theapparatus of claim 15, further comprising: a second voltage pinconfigured to couple the apparatus to a second voltage source; a thirdtransistor of the plurality of transistors comprising a gate that isconfigured as a first input of the apparatus, a first node of the thirdtransistor that is coupled with the second node of the first transistor,and a second node of the third transistor; a fourth transistor of theplurality of transistors comprising a gate that is configured as asecond input of the apparatus, a first node of the fourth transistorthat is coupled with the second node of the second transistor, and asecond node of the fourth transistor; and a fifth transistor configuredto couple the second node of the third transistor and the second node ofthe fourth transistor to the second voltage pin.
 19. The apparatus ofclaim 15, wherein the second configuration comprises: a first switchingcomponent of the plurality of switching components configured to couplea gate of the first transistor to a gate of the second transistor; and asecond switching component of the plurality of switching componentsconfigured to couple the gate of the first transistor to the second nodeof the first transistor.
 20. The apparatus of claim 19, wherein thesecond configuration comprises: a third switching component of theplurality of switching components configured to isolate the gate of thefirst transistor from the first voltage pin; a fourth switchingcomponent of the plurality of switching components configured to isolatethe gate of the second transistor from the first voltage pin; a fifthswitching component of the plurality of switching components configuredto isolate the gate of the first transistor from the second node of thesecond transistor; and a sixth switching component of the plurality ofswitching components configured to isolate the gate of the secondtransistor from the second node of the first transistor.